Patents by Inventor David Seebacher
David Seebacher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11831279Abstract: In accordance with an embodiment, a method for operating a millimeter-wave power amplifier including an input transistor having an output node coupled to a load path of a cascode transistor includes: receiving a millimeter-wave transmit signal at a control node of the input transistor; amplifying the millimeter-wave transmit signal to form an output signal; providing the output signal to a load coupled to an output node of the cascode transistor; and adjusting a first DC bias current of the input transistor to form a substantially constant second DC bias current of the cascode transistor.Type: GrantFiled: April 12, 2021Date of Patent: November 28, 2023Assignee: Infineon Technologies AGInventors: David Seebacher, Matteo Bassi, Dmytro Cherniak, Fabio Padovan
-
Publication number: 20220329206Abstract: In accordance with an embodiment, a method for operating a millimeter-wave power amplifier including an input transistor having an output node coupled to a load path of a cascode transistor includes: receiving a millimeter-wave transmit signal at a control node of the input transistor; amplifying the millimeter-wave transmit signal to form an output signal; providing the output signal to a load coupled to an output node of the cascode transistor; and adjusting a first DC bias current of the input transistor to form a substantially constant second DC bias current of the cascode transistor.Type: ApplicationFiled: April 12, 2021Publication date: October 13, 2022Inventors: David Seebacher, Matteo Bassi, Dmytro Cherniak, Fabio Padovan
-
Patent number: 11430744Abstract: In sonic examples, a method includes pre-stressing a flange, heating the flange to a die-attach temperature, and attaching a die to the flange at the die-attach temperature using a die-attach material. In some examples, the flange includes a metal material, the die-attach temperature may be at least two hundred degrees Celsius, and the die-attach material may include solder and/or an adhesive. In some examples, the method includes cooling the semiconductor die and metal flange to a room temperature after attaching the semiconductor die to the metal flange at the die-attach temperature using a die-attach material.Type: GrantFiled: August 10, 2017Date of Patent: August 30, 2022Assignee: Cree, Inc.Inventors: David Seebacher, Christian Schuberth, Peter Singerl, Alexander Komposch
-
Patent number: 10958224Abstract: Devices and methods for generating a bias voltage for a transceiver operating in time division multiplexing operation, and corresponding transceivers are provided. In this case, the bias voltage is controlled in guard intervals between transmission and reception of signals by the transceiver.Type: GrantFiled: June 16, 2020Date of Patent: March 23, 2021Assignee: Infineon Technologies AGInventors: David Seebacher, Pantelis Sarais, Peter Singerl, Herwig Wappis
-
Patent number: 10930990Abstract: A device includes at least one electrically conductive structure and at least one stripline. The stripline includes stripline sections that are connected to one another in a series connection between a first terminal and a second terminal. A first subset of the stripline sections is arranged on a first side of the conductive structure and a second subset of the stripline sections is arranged on a second side of the conductive structure. The device also includes at least one conductive connection between the first subset of the stripline sections and the second subset of the stripline sections, wherein the at least one conductive connection is isolated from the at least one electrically conductive structure.Type: GrantFiled: February 15, 2019Date of Patent: February 23, 2021Assignee: INFINEON TECHNOLOGIES AGInventors: David Seebacher, Andrea Del Chiaro, Christian Schuberth, Peter Singerl, Ji Zhao
-
Publication number: 20200313635Abstract: Devices and methods for generating a bias voltage for a transceiver operating in time division multiplexing operation, and corresponding transceivers are provided. In this case, the bias voltage is controlled in guard intervals between transmission and reception of signals by the transceiver.Type: ApplicationFiled: June 16, 2020Publication date: October 1, 2020Inventors: David Seebacher, Pantelis Sarais, Peter Singerl, Herwig Wappis
-
Patent number: 10778156Abstract: A circuit includes a first power transistor stage internally configured to function as a voltage-controlled current source, a second power transistor stage having an input impedance which varies as a function of input power and an interstage matching network coupling an output of the first power transistor stage to an input of the second power transistor stage. The interstage matching network is configured to provide impedance inversion between the input of the second power transistor stage and the output of the first power transistor stage. The impedance inversion provided by the interstage matching network transforms the first power transistor stage from functioning as a voltage-controlled current source to functioning as a voltage-controlled voltage source at the input of the second power transistor stage.Type: GrantFiled: June 20, 2017Date of Patent: September 15, 2020Assignee: Infineon Technologies AGInventors: David Seebacher, Christian Schuberth, Peter Singerl, Ji Zhao
-
Patent number: 10763228Abstract: Devices including a transistor having a parasitic capacitance between a control terminal and a load terminal of a first type are provided. Furthermore, the devices include advantageously arranged inductances which are electromagnetically coupled to one another and are configured at least partly to compensate for an effect of the parasitic capacitance in a range around a resonant frequency.Type: GrantFiled: December 21, 2018Date of Patent: September 1, 2020Assignee: Infineon Technologies AGInventors: David Seebacher, Andrea Del Chiaro, Peter Singerl, Ji Zhao
-
Patent number: 10741476Abstract: A passive electrical component includes a substrate. A first metallization layer is formed on the substrate. A first dielectric layer is formed on the first metallization layer The first dielectric layer has a lower thermal conductivity than the substrate. A second metallization layer is formed on the first dielectric layer. An electrically conductive via provides an electrical connection between a first section of the first metallization layer and a second section of the second metallization layer. A thermally conductive via provides a thermally conductive path between the second section and the substrate. The thermally conductive via provides an open circuit termination to the second section of the second metallization layer.Type: GrantFiled: April 19, 2017Date of Patent: August 11, 2020Assignee: Infineon Technologies AGInventors: Christian Schuberth, David Seebacher
-
Patent number: 10727793Abstract: Devices and methods for generating a bias voltage for a transceiver operating in time division multiplexing operation, and corresponding transceivers are provided. In this case, the bias voltage is controlled in guard intervals between transmission and reception of signals by the transceiver.Type: GrantFiled: August 21, 2018Date of Patent: July 28, 2020Assignee: Infineon Technologies AGInventors: David Seebacher, Pantelis Sarais, Peter Singerl, Herwig Wappis
-
Publication number: 20190280360Abstract: A device includes at least one electrically conductive structure and at least one stripline. The stripline includes stripline sections that are connected to one another in a series connection between a first terminal and a second terminal. A first subset of the stripline sections is arranged on a first side of the conductive structure and a second subset of the stripline sections is arranged on a second side of the conductive structure. The device also includes at least one conductive connection between the first subset of the stripline sections and the second subset of the stripline sections, wherein the at least one conductive connection is isolated from the at least one electrically conductive structure.Type: ApplicationFiled: February 15, 2019Publication date: September 12, 2019Inventors: David Seebacher, Andrea Del Chiaro, Christian Schuberth, Peter Singerl, Ji Zhao
-
Publication number: 20190198465Abstract: Devices including a transistor having a parasitic capacitance between a control terminal and a load terminal of a first type are provided. Furthermore, the devices include advantageously arranged inductances which are electromagnetically coupled to one another and are configured at least partly to compensate for an effect of the parasitic capacitance in a range around a resonant frequency.Type: ApplicationFiled: December 21, 2018Publication date: June 27, 2019Inventors: David Seebacher, Andrea Del Chiaro, Peter Singerl, Ji Zhao
-
Publication number: 20190058448Abstract: Devices and methods for generating a bias voltage for a transceiver operating in time division multiplexing operation, and corresponding transceivers are provided. In this case, the bias voltage is controlled in guard intervals between transmission and reception of signals by the transceiver.Type: ApplicationFiled: August 21, 2018Publication date: February 21, 2019Inventors: David Seebacher, Pantelis Sarais, Peter Singerl, Herwig Wappis
-
Publication number: 20190051617Abstract: In sonic examples, a method includes pre-stressing a flange, heating the flange to a die-attach temperature, and attaching a die to the flange at the die-attach temperature using a die-attach material. In some examples, the flange includes a metal material, the die-attach temperature may be at least two hundred degrees Celsius, and the die-attach material may include solder and/or an adhesive. In some examples, the method includes cooling the semiconductor die and metal flange to a room temperature after attaching the semiconductor die to the metal flange at the die-attach temperature using a die-attach material.Type: ApplicationFiled: August 10, 2017Publication date: February 14, 2019Inventors: David Seebacher, Christian Schuberth, Peter Singerl, Alexander Komposch
-
Patent number: 10171039Abstract: A peaking amplifier is disclosed. The peaking amplifier includes a driver stage, a final stage, and an interstage matching network. The driver stage has a load impedance and is configured to generate a driver output based on an input signal. The final stage has a final stage input impedance and is configured to generate a peaking output based on the driver output. The interstage matching network is coupled to the driver stage and the final stage. The interstage matching network is configured to transform the final stage input impedance to the load impedance for the driver stage when the peaking amplifier is ON and to provide a short to an input of the final stage when the peaking amplifier is in an OFF state.Type: GrantFiled: August 31, 2015Date of Patent: January 1, 2019Assignee: Infineon Technologies AGInventors: David Seebacher, Christian Schuberth, Peter Singerl, Tim Canning, Richard Wilson, Haedong Jang
-
Publication number: 20180367104Abstract: A circuit includes a first power transistor stage internally configured to function as a voltage-controlled current source, a second power transistor stage having an input impedance which varies as a function of input power and an interstage matching network coupling an output of the first power transistor stage to an input of the second power transistor stage. The interstage matching network is configured to provide impedance inversion between the input of the second power transistor stage and the output of the first power transistor stage. The impedance inversion provided by the interstage matching network transforms the first power transistor stage from functioning as a voltage-controlled current source to functioning as a voltage-controlled voltage source at the input of the second power transistor stage.Type: ApplicationFiled: June 20, 2017Publication date: December 20, 2018Inventors: David Seebacher, Christian Schuberth, Peter Singerl, Ji Zhao
-
Publication number: 20180308919Abstract: A passive electrical component includes a substrate. A first metallization layer is formed on the substrate. A first dielectric layer is formed on the first metallization layer The first dielectric layer has a lower thermal conductivity than the substrate. A second metallization layer is formed on the first dielectric layer. An electrically conductive via provides an electrical connection between a first section of the first metallization layer and a second section of the second metallization layer. A thermally conductive via provides a thermally conductive path between the second section and the substrate. The thermally conductive via provides an open circuit termination to the second section of the second metallization layer.Type: ApplicationFiled: April 19, 2017Publication date: October 25, 2018Inventors: Christian Schuberth, David Seebacher
-
Patent number: 10069662Abstract: A pulse width modulation system comprises an analog component and a digital component. The analog component operates to separate a local oscillator signal with different phase shifts and introduce an offset (i.e., a time delay) to analog signals being receive at an input with a tuning operation that fine tunes in the analog signals in the analog (continuous time) domain. The analog component comprises a plurality of analog delay lines that respectively process carrier signals having a different phase shifts. Digital delay lines convert the analog signals to digital square waves with the same time delay and at the same resolution as the analog output signal.Type: GrantFiled: November 10, 2015Date of Patent: September 4, 2018Assignee: Infineon Technologies AGInventors: Yannis Papananos, David Seebacher, Nikolaos Alexiou, Franz Dielacher, Konstantinos Galanopoulos, Peter Singerl, Marc Tiebout
-
Patent number: 10038404Abstract: Techniques are provided for adapting a bias provided to a radio frequency (RF) power amplifier (PA), so as to achieve linear operation over a wide range of conditions. The techniques use open-loop temperature compensation based upon a sensed current during periods when the RF PA is active and inactive. A closed-loop control technique is enabled when the RF PA is inactive. The combined control techniques compensate for temperature variation as well as long-term drift of the semiconductor properties of the devices within the RF PA.Type: GrantFiled: June 22, 2017Date of Patent: July 31, 2018Assignee: Infineon Technologies AGInventors: Pantelis Sarais, David Seebacher, Peter Singerl, Herwig Wappis
-
Publication number: 20180175811Abstract: An amplifier circuit includes an RF input port, an RF output port, a reference potential port, and an RF amplifier having an input terminal and a first output terminal. An output impedance matching network electrically couples the first output terminal to the RF output port. A first inductor is electrically connected in series between the first output terminal and the RF output port, a first LC resonator is directly electrically connected between the first output terminal and the reference potential port, and a second LC resonator is directly electrically connected between the first output terminal and the reference potential port. The first LC resonator is configured to compensate for an output capacitance of the RF amplifier at a center frequency of the RF signal. The second LC resonator is configured to compensate for a second order harmonic of the RF signal.Type: ApplicationFiled: December 21, 2016Publication date: June 21, 2018Inventors: Timothy Canning, Richard Wilson, Haedong Jang, David Seebacher, Christian Schuberth, Rongguo Zhou, Bayaner Arigong