Abstract: There is provided a filter assembly arranged to be mounted over the air inlet of a fan assembly, the filter assembly comprising a filter frame arranged to support one or more filter media. The filter frame is provided with a first engagement member on a first edge of the filter frame and a second engagement member on a second edge of the filter frame, the first edge being opposite to the second edge. The first engagement member and the second engagement member are each configured to be engaged by a respective retention assembly when mounted on the fan assembly.

Abstract: There is provided a filter assembly arranged to be mounted over the air inlet of a fan assembly, the filter assembly comprising a filter frame arranged to support one or more filter media. The filter frame is provided with a first engagement member on a first edge of the filter frame and a second engagement member on a second edge of the filter frame, the first edge being opposite to the second edge. The first engagement member and the second engagement member are each configured to be engaged by a respective retention assembly when mounted on the fan assembly.

Abstract: As fast and powerful commodity processors have been developed, it has become practical to emulate on platforms built using commodity processors the proprietary hardware systems of powerful older computers. High performance is typically a key requirement for a system even when built using emulation software. In a hardware design many special cases and conditions which may cause exceptions are detected by logic operating in parallel with the instruction execution. In software these checks can cost extra cycles of processor time during emulation of each instruction and be a significant detriment to performance. Avoiding some of these checks by relying upon the underlying hardware checks of the host system and then using a signal handler and special software to recover from these signals is a way to improve the performance and simplify the coding of the software emulation system.

Abstract: As manufacturers of very fast and powerful commodity processors continue to improve the capabilities of their products, it has become practical to emulate the proprietary hardware and operating systems of powerful older computers on platforms built using commodity processors such that the manufacturers of the older computers can provide new systems which allow their customers to continue to use their highly-regarded proprietary legacy software on state-of-the-art new computer systems by emulating the older computer in software that runs on the new systems. In an example of the subject invention, a 64-bit Cobol Virtual Machine instruction provides the capability of adding to or improving the performance of legacy 36-bit Cobol code. Legacy Cobol instructions can be selectively diverted, in the host CPU, to a 64 bit Virtual Machine Implementation.

Abstract: As fast and powerful commodity processors have been developed, it has become practical to emulate the proprietary hardware systems of powerful older computers on platforms built using commodity processors. The systems being emulated are often large mainframe computers with large numbers of disks, communications systems and other attached hardware. Because of the size and expense, and also because databases involved must reside in only one location, it is difficult to replicate these systems for testing, development, debug or for providing alternative options to customers. A method for providing a single emulated computer system which provides for multiple views or options in control of the emulator is disclosed in which the options are dependent and selected based on job or user basis. The mechanism continues to provide for high performance and a single copy of the operating system with multiple processes, jobs and threads being emulated under user controlled parameters.

Abstract: As fast and powerful commodity processors have been developed, it has become practical to emulate on platforms built using commodity processors the proprietary hardware systems of powerful older computers that have been developed and honed over many years. The reliability and robustness of the legacy system and its emulated replacement are of utmost importance. Since the emulation system software is new and complex it may have undiscovered errors in coding which if encountered may result in an abort of the emulation program itself. This software emulation program abort is akin to a logic failure or bug in the legacy system hardware. Utilizing a signal handler in analysis and recovery from coding errors, while not taking greater risk of data corruption, increases the stability and robustness of the emulated computer system and is akin to hardware error correction in the legacy system hardware design.

Abstract: A methodology for improving the timing of specific critical paths in a Field Programmable Gate Array (FPGA) implementation of a logic circuit without significantly affecting the timing of other logic paths. The method utilizes logic replication and specific guidelines for placement of the logic gates involved in a critical path to optimize the timing of that critical path. The logic gates involved in a critical path are either replicated and placed, or simply moved, in order to implement the desired logic with nearly the shortest total distance for routing of signals involved in the critical path. The optimization is carried out with relatively little impact on the timing of other paths and is applicable to FPGAs in which the signal delay between any source and gate is relatively independent of the fanout of the source signal to any other loads.

Abstract: A process for determining the optimum load driving capacity for each driving node in a complex logic circuit is disclosed. First, the logic equations of the logic circuit are extracted from a circuit description. Then, the fan-out of each driving node is analyzed to determine if the total number of pass transistor loads of the analyzed node is excessive compared to a predetermined driving capacity. For each flagged node, logic equations are added which represent the sum of the node's pass transistor loads, and further logic equations are added to compare the number of pass transistors turned on from one to the absolute maximum for the node. Then, a formal proof program is used to analyze the logic circuit and determine which of the comparators have a true output.