Abstract: A regulator circuit includes a multiphase ramp generator circuit, an amplifier circuit configured to receive a plurality of phase sense signals and provide a plurality of respective error signals, and an adder circuit configured to receive the error signals and ramp generator signals. The ramp generator signals are received from the multiphase ramp generator circuit and the adder circuit is configured to provide a plurality of respective adjusted ramp generator signals. The regulator can be a multiphase switching regulator circuit.

Abstract: A regulator circuit includes a multiphase ramp generator circuit, an amplifier circuit configured to receive a plurality of phase sense signals and provide a plurality of respective error signals, and an adder circuit configured to receive the error signals and ramp generator signals. The ramp generator signals are received from the multiphase ramp generator circuit and the adder circuit is configured to provide a plurality of respective adjusted ramp generator signals. The regulator can be a multiphase switching regulator circuit.

Abstract: A circuit comprising a first transistor group configured to electrically isolate, at least in part, a second transistor group from an input voltage; the second transistor group configured to provide voltage protection to a third transistor group; and the third transistor group configured to switch on and off.

Abstract: A circuit comprising a first transistor group configured to electrically isolate, at least in part, a second transistor group from an input voltage; the second transistor group configured to provide voltage protection to a third transistor group; and the third transistor group configured to switch on and off.

Abstract: A circuit comprising a first transistor group configured to electrically isolate, at least in part, a second transistor group from an input voltage; the second transistor group configured to provide voltage protection to a third transistor group; and the third transistor group configured to switch on and off.

Abstract: A circuit comprising a first transistor group configured to electrically isolate, at least in part, a second transistor group from an input voltage; the second transistor group configured to provide voltage protection to a third transistor group; and the third transistor group configured to switch on and off.

Abstract: A switching regulator automatically operates in pulse width modulation (“PWM”) mode for high load currents and in burst mode for low load currents. The switching regulator includes a pair of switches to provide a regulated current to a load. The switching regulator further includes a multi-input comparator. A first input of the comparator is coupled to an output of the pair of switches. A second input of the comparator is coupled to a filtered version of the output and a third input is coupled to a reference waveform. The first, second and third inputs of the comparator form a combined input signal to the comparator. An output signal of the comparator is generated by comparing the combined input signal to a threshold of the comparator. The output signal determines a switching frequency of the pair of switches such that the switching frequency is automatically reduced when the load is decreased.

Abstract: A clock and data recovery system for detecting and resolving meta-stability conditions is provided. The clock and data recovery system includes a phase detector having logic configured to detect a meta-stability condition and to generate an output signal to mitigate the condition. The system can also include a time varying gain adjustment portion. This portion includes a gain control logic configured to determine and adjust system gain during reception of an incoming data stream. The system further includes a phase interpolator having increased linearity. The phase interpolator has a plurality of first branches having a differential transistor pair, a switch, and a current source, coupled between a first output and a first supply voltage and a plurality of second branches having a differential transistor pair, a switch, and a current source, coupled between a second output and the first supply voltage. The phase interpolator can also include an integrator portion.

Abstract: A differential line driver includes a plurality of driver cells. Control logic outputs positive and negative control signals to the driver cells so as to match a combined output impedance of the driver cells at (Vop, Von). Each driver cell includes an input Vip and an input Vin, an output Vop and an output Von, a first PMOS transistor and a first NMOS transistor having gates driven by the input Vip, and a second PMOS transistor and a second NMOS transistor having gates driven by the input Vin. A source of the first PMOS transistor is connected to a source of the second PMOS transistor. A source of the first NMOS transistor is connected to a source of the second NMOS transistor. First and second resistors are connected in series between the first PMOS transistor and the first NMOS transistor, and connected together at Von. Third and fourth resistors are connected in series between the second PMOS transistor and the second NMOS transistor, and connected together at Vop.

Abstract: A differential line driver includes a plurality of driver cells. Control logic outputs positive and negative control signals to the driver cells so as to match a combined output impedance of the driver cells at (Vop, Von). Each driver cell includes an input Vip and an input Vin, an output Vop and an output Von, a first PMOS transistor and a first NMOS transistor having gates driven by the input Vip, and a second PMOS transistor and a second NMOS transistor having gates driven by the input Vin. A source of the first PMOS transistor is connected to a source of the second PMOS transistor. A source of the first NMOS transistor is connected to a source of the second NMOS transistor. First and second resistors are connected in series between the first PMOS transistor and the first NMOS transistor, and connected together at Von. Third and fourth resistors are connected in series between the second PMOS transistor and the second NMOS transistor, and connected together at Vop.

Abstract: A differential line driver includes a plurality of driver cells. Control logic outputs positive and negative control signals to the driver cells so as to match a combined output impedance of the driver cells at (Vop, Von). Each driver cell includes an input Vip and an input Vin, an output Vop and an output Von, a first PMOS transistor and a first NMOS transistor having gates driven by the input Vip, and a second PMOS transistor and a second NMOS transistor having gates driven by the input Vin. A source of the first PMOS transistor is connected to a source of the second PMOS transistor. A source of the first NMOS transistor is connected to a source of the second NMOS transistor. First and second resistors are connected in series between the first PMOS transistor and the first NMOS transistor, and connected together at Von. Third and fourth resistors are connected in series between the second PMOS transistor and the second NMOS transistor, and connected together at Vop.

Abstract: A differential line driver includes a plurality of driver cells. Control logic outputs positive and negative control signals to the driver cells so as to match a combined output impedance of the driver cells at (Vop, Von). Each driver cell includes an input Vip and an input Vin, an output Vop and an output Von, a first PMOS transistor and a first NMOS transistor having gates driven by the input Vip, and a second PMOS transistor and a second NMOS transistor having gates driven by the input Vin. A source of the first PMOS transistor is connected to a source of the second PMOS transistor. A source of the first NMOS transistor is connected to a source of the second NMOS transistor. First and second resistors are connected in series between the first PMOS transistor and the first NMOS transistor, and connected together at Von. Third and fourth resistors are connected in series between the second PMOS transistor and the second NMOS transistor, and connected together at Vop.

Abstract: An operational amplifier with MOSFET's configured as capacitors provide frequency compensation over a large range of input frequencies is described. The operational amplifier has an differential amplifier stage with an inverting and an noninverting input. The difference of signals placed at the inverting and the noninverting inputs are amplified and place at the input of a folded cascode amplifier stage. The output of the folded cascode amplifier stage is the input to a linear amplifier stage. The output of the linear amplifier stage is connected to external loading circuitry. A first frequency compensation capacitor is connected between the output of the linear amplifier stage and a noninverted input of the folded cascode amplifier. A second frequency compensation capacitor is connected between the output of the linear amplifier stage and a virtual ground within the folded cascode amplifier stage.