Abstract: A device may perform a first full-matrix optical scan covering a first scan area and having a first resolution to identify a first maximum power spot within a region where the optical signal is detected when a first MEMS micro-mirror and a second MEMS micro-mirror are concurrently at their respective first maximum power positions. The device may perform a second full-matrix optical scan centered around the first maximum power spot, the second full-matrix optical scan covering a second scan area smaller than the first scan area and having a second resolution finer than the first resolution. The device may identify a second maximum power spot within the first maximum power spot when the first MEMS micro-mirror and the second MEMS micro-mirror are concurrently at their respective second maximum power positions. The device may lock the respective second maximum power positions of the first MEMS micro-mirror and the second MEMS micro-mirror.

Abstract: A passive alignment system includes a base substrate, a lower cladding layer disposed over the base substrate, a core layer disposed over the lower cladding layer, and an upper cladding layer disposed over the core layer. The passive alignment system also includes one or more planar waveguides including one or more cores formed in a first portion of the core layer disposed over a first portion of the lower cladding layer, the one or more cores extending from a transmitting end to a receiving end in an X-Y plane. The passive alignment system also includes at least one alignment feature formed in a second portion of the core layer disposed over a second portion of the lower cladding layer and configured to align with an optical receiving or transmitting device. The at least one alignment feature aligns the optical receiving or transmitting device with the one or more planar waveguides.

Abstract: In one embodiment, an apparatus includes a plurality of layers in a circuit board, each of the layers comprising a fiber weave, two plated holes extending through the layers and connecting two or more of the layers, and a non-plated hole interposed between the plated holes. The non-plated hole passes through a potential CAF (Conductive Anodic Filament) migration path along the fiber weave to prevent CAF formation between the plated holes.

Abstract: A printed circuit board (PCB) stack-up has a signal via configured to transmit a signal through at least two different layers of the PCB stack-up, a reference structure that is at least a portion of a return path for the signal; and an unplated via disposed in an area surrounding the signal via. The unplated via is disposed in the area surrounding the signal via to improve the characteristic impedance of the signal via.

Abstract: A printed circuit board (PCB) may be provided. The PCB may comprise a first electrically conductive layer comprising a first signal layer. Also, the PCB may comprise a second electrically conductive layer comprising a second signal layer or a plane layer associated with the first signal layer. The PCB may further comprise a waveguide layer disposed between the first electrically conductive layer and adjacent the second electrically conductive layer. The waveguide layer may transmit optical signals and function as a dielectric between the first electrically conductive layer and the second electrically conductive layer.

Abstract: In one embodiment, a method includes capturing an image of a piece of a printed circuit board (PCB) that includes at least one inner layer having a metal foil portion. The piece of the PCB includes a cross-section of the inner layer having the metal foil portion. The method also includes determining a surface roughness of the metal foil portion, wherein determining the surface roughness of the metal foil portion includes processing the image.

Abstract: A printed circuit board (PCB) stack-up has a signal via configured to transmit a signal through at least two different layers of the PCB stack-up, a reference structure that is at least a portion of a return path for the signal; and an unplated via disposed in an area surrounding the signal via. The unplated via is disposed in the area surrounding the signal via to improve the characteristic impedance of the signal via.