Patents by Inventor David Shaddock
David Shaddock has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130105993Abstract: There is set forth herein a semiconductor assembly including an integrated circuit and a set of springs extending from the integrated circuit that can be adapted for connection to an external article. The external article can be e.g. an integrated circuit or a printed circuit board. On connection of the semiconductor assembly to an external article there can be defined a semiconductor assembly comprising the integrated circuit the set of springs and the external article. The set of springs can be metal nanospring array can formed by GLAD (Glancing angle deposition) process. In one embodiment, the nanospring array can be GLAD formed on a substrate and then applied to the integrated circuit. In one embodiment, the nanospring array can be GLAD formed on the integrated circuit.Type: ApplicationFiled: October 28, 2011Publication date: May 2, 2013Applicant: GENERAL ELECTRIC COMPANYInventors: Raj BAHADUR, David SHADDOCK, Binoy SHAH
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Publication number: 20070005294Abstract: A clearance measurement system is provided. The clearance measurement system includes a reference geometry disposed on a first object having an otherwise continuous surface geometry and a sensor disposed on a second object, wherein the sensor is configured to generate a first signal representative of a first sensed parameter from the first object and a second signal representative of a second sensed parameter from the reference geometry. The clearance measurement system also includes a processing unit configured to process the first and second signals to estimate a clearance between the first and second objects based upon a measurement difference between the first and second sensed parameters.Type: ApplicationFiled: June 27, 2005Publication date: January 4, 2007Inventors: Emad Andarawis, Mahadevan Balasubramaniam, Todd Anderson, Samhita Dasgupta, David Shaddock, Shobhana Mani, Jie Jiang
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Publication number: 20060289308Abstract: An exhaust gas sensor system includes an inner chamber disposed around a sensor element. The inner chamber has either a cylindrical shape or a frusto-conical shape. The system further includes an outer chamber disposed substantially around the inner chamber to redirect a flow of an exhaust gas stream having an original direction by allowing the exhaust gas stream to strike a surface of the inner chamber to change the original direction of the flow to a substantially perpendicular direction relative to the original direction, then to substantially reverse the substantially perpendicular direction of the flow to create a substantially reversed flow within the inner chamber. Alternately the exhaust sensor system includes a sintered metal filter that prevents exhaust gas particles from fouling a sensor element.Type: ApplicationFiled: June 24, 2005Publication date: December 28, 2006Inventors: David Shaddock, Ganapathisubbu Sethuvenkatraman, Kunal Goray
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Publication number: 20060283255Abstract: A high-temperature pressure sensor that includes a dielectric layer. The pressure sensor also includes a substrate capable of withstanding temperatures greater than 450° C. without entering a phase change, at least one semiconducting material deposited on the sapphire substrate, and a silicon dioxide layer deposited over the semiconducting material. One aspect of the pressure sensor includes a second semiconducting material.Type: ApplicationFiled: August 25, 2006Publication date: December 21, 2006Inventors: Vinayak Tilak, Jie Jiang, David Shaddock, Stacey Kennerly, David Esler, Aaron Knobloch
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Publication number: 20060239813Abstract: A clearance sensing system for a rotating machine includes a plurality of sensor probes disposed within a stationary shroud of the rotating machine. Each of the plurality of sensor probes is adapted to measure a parameter indicative of an axial and a radial displacement of a rotating component within the shroud and to produce a signal that corresponds to the parameter. In certain embodiments, this parameter may include a capacitance between the rotating component and the sensor probe. The clearance sensing system further includes a circuit that receives the signal from each of the plurality of sensor probes and determines (a) the axial displacement of the rotating component within the shroud and (b) a radial displacement of the rotating component relative to the shroud.Type: ApplicationFiled: April 26, 2005Publication date: October 26, 2006Inventors: Minesh Shah, Mahadevan Balasubramaniam, Philip Beauchamp, Todd Anderson, Samhita Dasgupta, David Shaddock, Emad Andarawis
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Patent number: 6964877Abstract: Surface mount light emitting diode (LED) packages each contain a light emitting diode (LED) die (24). A plurality of arrays of openings are drilled into an electrically insulating sub-mount wafer (10). A metal is applied to the drilled openings to produce a plurality of via arrays (12). The LED dice (24) are flip-chip bonded onto a frontside (16) of the sub-mount wafer (10). The p-type and n-type contacts of each flip-chip bonded LED (24) electrically communicate with a solderable backside (18) of the sub-mount wafer (10) through a via array (12). A thermal conduction path (10, 12) is provided for thermally conducting heat from the flip-chip bonded LED dice (24) to the solderable backside (18) of the sub-mount wafer (10). Subsequent to the flip-chip bonding, the sub-mount wafer (10) is separated to produce the surface mount LED packages.Type: GrantFiled: April 27, 2004Date of Patent: November 15, 2005Assignee: GELcore, LLCInventors: Chen-Lun Hsing Chen, Stanton Weaver, Jr., Ivan Eliashevich, Sebastien Libon, Mehmet Arik, David Shaddock
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Publication number: 20050097941Abstract: A gas sensor device including a semiconductor substrate; one or more catalytic gate-electrodes deposited on a surface of the semiconductor substrate; one or more ohmic contacts deposited on the surface of the semiconductor substrate and a passivation layer deposited on at least a portion of the surface; wherein the semiconductor substrate includes a material selected from the group consisting of silicon carbide, diamond, Group III nitrides, alloys of Group III nitrides, zinc oxide, and any combinations thereof.Type: ApplicationFiled: November 12, 2003Publication date: May 12, 2005Inventors: Peter Sandvik, Vinayak Tilak, Jesse Tucker, Stanton Weaver, David Shaddock, Jonathan Male, John Lemmon, Mark Woodmansee, Venkatesan Manivannan, Deborah Haitko
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Publication number: 20040203189Abstract: Surface mount light emitting diode (LED) packages each contain a light emitting diode (LED) die (24). A plurality of arrays of openings are drilled into an electrically insulating sub-mount wafer (10). A metal is applied to the drilled openings to produce a plurality of via arrays (12). The LED dice (24) are flip-chip bonded onto a frontside (16) of the sub-mount wafer (10). The p-type and n-type contacts of each flip-chip bonded LED (24) electrically communicate with a solderable backside (18) of the sub-mount wafer (10) through a via array (12). A thermal conduction path (10, 12) is provided for thermally conducting heat from the flip-chip bonded LED dice (24) to the solderable backside (18) of the sub-mount wafer (10). Subsequent to the flip-chip bonding, the sub-mount wafer (10) is separated to produce the surface mount LED packages.Type: ApplicationFiled: April 27, 2004Publication date: October 14, 2004Applicant: GELcore LLCInventors: Chen-Lun Hsing Chen, Stanton Weaver, Ivan Eliashevich, Sebastien Libon, Mehmet Arik, David Shaddock
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Publication number: 20040188696Abstract: Surface mount light emitting diode (LED) packages each contain a light emitting diode (LED) die (24). A plurality of arrays of openings are drilled into an electrically insulating sub-mount wafer (10). A metal is applied to the drilled openings to produce a plurality of via arrays (12). The LED dice (24) are flip-chip bonded onto a frontside (16) of the sub-mount wafer (10). The p-type and n-type contacts of each flip-chip bonded LED (24) electrically communicate with a solderable backside (18) of the sub-mount wafer (10) through a via array (12). A thermal conduction path (10, 12) is provided for thermally conducting heat from the flip-chip bonded LED dice (24) to the solderable backside (18) of the sub-mount wafer (10). Subsequent to the flip-chip bonding, the sub-mount wafer (10) is separated to produce the surface mount LED packages.Type: ApplicationFiled: March 28, 2003Publication date: September 30, 2004Applicant: GELcore, LLCInventors: Chen-Lun Hsing Chen, Stanton Weaver, Ivan Eliashevich, Sebastien Libon, Mehmet Arik, David Shaddock