Abstract: In some embodiments, an integrated circuit may include a substrate and a memory array disposed on the substrate, where the memory array includes a plurality of discrete memory banks. The integrated circuit may also include a processing array disposed on the substrate, where the processing array includes a plurality of processor subunits, each one of the plurality of processor subunits being associated with one or more discrete memory banks among the plurality of discrete memory banks. The integrated circuit may also include a controller configured to implement at least one security measure with respect to an operation of the integrated circuit and take one or more remedial actions if the at least one security measure is triggered.

Abstract: Disclosed is a self-sanitizing enclosure for installation onto a table-top. The self-sanitizing enclosure includes a UVC light source, where the UVC radiation emitted from the UVC light source is configured to sterilize components that are stored within the self-sanitizing enclosure.

Abstract: In some embodiments, an integrated circuit may include a substrate and a memory array disposed on the substrate, where the memory array includes a plurality of discrete memory banks. The integrated circuit may also include a processing array disposed on the substrate, where the processing array includes a plurality of processor subunits, each one of the plurality of processor subunits being associated with one or more discrete memory banks among the plurality of discrete memory banks. The integrated circuit may also include a controller configured to implement at least one security measure with respect to an operation of the integrated circuit and take one or more remedial actions if the at least one security measure is triggered.

Abstract: A modular partition system is based upon a panel frame structure formed of vertical members of substantially lesser thickness than the panels to be formed, which may be joined end-to-end in a modular manner, and side-by-side to join vertical ends of adjacent panels, and horizontal C-section rails secured to opposite sides of the vertical rails with mouths of the C-sections facing outwardly. Cladding panels are secured by vertically-spaced sets of spring clips engaging respectively upper and lower surfaces of vertically-spaced horizontal rails, and panels and other furnishings are secured to brackets engaged within the C-section of horizontal rails. The relationship of the horizontal and vertical members allows for easy cabling, and the use of the clamps permits panels and furnishings to be located without substantial regard to the horizontal modularity of the system. The basic panelling system requires a minimum number of different modular parts.

Abstract: An apparatus and method for implementing watchpoints and breakpoints in a data processing system (110). In one embodiment, a pipelined processor (110) performs each instruction of a program. One or more watchpoints are associated with the instructions. The processor includes a history buffer (50) for storing processor state values at the time when each of the instructions was executed, until a predetermined time. Watchpoint information associated with a particular watchpoint is also stored in the history buffer (50), in association with the processor state values, such that the processor state is changed and the watchpoint is announced at the predetermined time. The watchpoint information may include increment/decrement information for one or more counters (41, 42). Breakpoint information may also be stored in history buffer (50).

Abstract: An interrupt mechanism allows an interrupt request signal to be adjusted to any priority level specified by the user and provides to a CPU an encoded interrupt signal which either indicates that the interrupt priority has been adjusted or identifies a highest prioritized interrupt request when no adjustment in priority is made. A first logic circuit functions to receive a priority adjust request signal and compares the adjust signal with one or more interrupt signals to determine if an adjustment is required. A second logic circuit functions to identify the highest prioritized interrupt request of a plurality of interrupt requests and provides the encoded interrupt signal in response thereto. In one form, the encoded interrupt signal is translated into a value for use in a software exception processing routine within the CPU. The software exception processing routine can perform a variety of user specified functions with the encoded adjusted priority interrupt signal.