Patents by Inventor David Shreiner

David Shreiner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9619937
    Abstract: An apparatus for processing primitives in a tile-based graphics processing system includes processing circuitry which is configured to determine, for a group of plural primitives, the rendering tiles that the group of primitives should be processed for. The processing circuitry is also configured to store, for the group of primitives, a data entry containing an indication of the identity of the plurality of primitives in the group of primitives, and an indication of the rendering tiles that it has been determined the group of primitives should be processed for.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: April 11, 2017
    Assignee: ARM LIMITED
    Inventors: Hakan Persson, David Shreiner
  • Publication number: 20160260249
    Abstract: An apparatus for processing primitives in a tile-based graphics processing system includes processing circuitry which is configured to determine, for a group of plural primitives, the rendering tiles that the group of primitives should be processed for. The processing circuitry is also configured to store, for the group of primitives, a data entry containing an indication of the identity of the plurality of primitives in the group of primitives, and an indication of the rendering tiles that it has been determined the group of primitives should be processed for.
    Type: Application
    Filed: March 5, 2015
    Publication date: September 8, 2016
    Inventors: Hakan Persson, David Shreiner
  • Patent number: 8194083
    Abstract: A plurality of vertex or fragment processors on a graphics processor perform computations. Each vertex or fragment processor is capable of executing a separate program to compute a specific result. A combiner manages the combination of the results from the respective processors, and produces a final transformed vertex or pixel value. The vertex or fragment processors and the combiner can be programmable to modify their operations. As such, the vertex or fragment processors can operate in a parallel or serial configuration, or both. The combiner manages and resolves the operations of the serial and/or parallel configurations. A synchronization barrier enables the combiner to perform data-dependency analysis to determine the timing and ordering of the respective processors' execution. A transformation module can include one or more programmable vertex processors that transforms three-dimensional geometric data into fragments.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: June 5, 2012
    Assignee: Graphics Properties Holdings, Inc.
    Inventor: David Shreiner
  • Publication number: 20110050697
    Abstract: A plurality of vertex or fragment processors on a graphics processor perform computations. Each vertex or fragment processor is capable of executing a separate program to compute a specific result. A combiner manages the combination of the results from the respective processors, and produces a final transformed vertex or pixel value. The vertex or fragment processors and the combiner can be programmable to modify their operations. As such, the vertex or fragment processors can operate in a parallel or serial configuration, or both. The combiner manages and resolves the operations of the serial and/or parallel configurations. A synchronization barrier enables the combiner to perform data-dependency analysis to determine the timing and ordering of the respective processors' execution. A transformation module can include one or more programmable vertex processors that transforms three-dimensional geometric data into fragments.
    Type: Application
    Filed: November 8, 2010
    Publication date: March 3, 2011
    Applicant: Graphic Properties Holdings, Inc.
    Inventor: David SHREINER
  • Patent number: 7830390
    Abstract: A plurality of vertex or fragment processors on a graphics processor perform computations. Each vertex or fragment processor is capable of executing a separate program to compute a specific result. A combiner manages the combination of the results from the respective processors, and produces a final transformed vertex or pixel value. The vertex or fragment processors and the combiner can be programmable to modify their operations. As such, the vertex or fragment processors can operate in a parallel or serial configuration, or both. The combiner manages and resolves the operations of the serial and/or parallel configurations. A synchronization barrier enables the combiner to perform data-dependency analysis to determine the timing and ordering of the respective processors' execution. A transformation module can include one or more programmable vertex processors that transforms three-dimensional geometric data into fragments.
    Type: Grant
    Filed: July 19, 2005
    Date of Patent: November 9, 2010
    Assignee: Graphics Properties Holdings, Inc.
    Inventor: David Shreiner
  • Patent number: 7716683
    Abstract: A method and apparatus forward a hardware call from a driver to graphics hardware via a virtual connection. Specifically, the method and apparatus process graphical data in a system having the driver, which produces a hardware call for the controlling the operation of the graphics hardware. As noted above, the method and apparatus first establish the virtual connection between the driver and the graphics hardware. Next, the hardware call is forwarded to the graphics hardware via the virtual connection.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: May 11, 2010
    Assignee: Graphics Properties Holdings, Inc.
    Inventors: Hansong Zhang, David Shreiner
  • Patent number: 7460126
    Abstract: A system and method for distributing data (e.g., imaging data such as pixels, or 3D graphics data such as points, lines, or polygons) from a single or a small number of data sources to a plurality of graphical processing units (graphics processors) for processing and display is presented. The system and method provide a pipelined and multithreaded approach that prioritizes movement of the data through a high-speed multiprocessor system (or a high-speed system of networked computers), according to the system topology. Multiple threads running on multiple processors in shared memory move the data from a storage device (e.g., a disk array), through the high-speed multiprocessor system, to graphics processor memory for display and optional processing through fragment programming. The data can also be moved in the reverse direction, back through the high-speed multiprocessor system, for storage on the disk array.
    Type: Grant
    Filed: August 24, 2005
    Date of Patent: December 2, 2008
    Assignee: Silicon Graphics, Inc.
    Inventors: Brad Grantham, David Shreiner, Alan Commike
  • Publication number: 20070018990
    Abstract: A plurality of vertex or fragment processors on a graphics processor perform computations. Each vertex or fragment processor is capable of executing a separate program to compute a specific result. A combiner manages the combination of the results from the respective processors, and produces a final transformed vertex or pixel value. The vertex or fragment processors and the combiner can be programmable to modify their operations. As such, the vertex or fragment processors can operate in a parallel or serial configuration, or both. The combiner manages and resolves the operations of the serial and/or parallel configurations. A synchronization barrier enables the combiner to perform data-dependency analysis to determine the timing and ordering of the respective processors' execution. A transformation module can include one or more programmable vertex processors that transforms three-dimensional geometric data into fragments.
    Type: Application
    Filed: July 19, 2005
    Publication date: January 25, 2007
    Applicant: Silicon Graphics, Inc.
    Inventor: David Shreiner
  • Publication number: 20060146058
    Abstract: A method and apparatus forward a hardware call from a driver to graphics hardware via a virtual connection. Specifically, the method and apparatus process graphical data in a system having the driver, which produces a hardware call for the controlling the operation of the graphics hardware. As noted above, the method and apparatus first establish the virtual connection between the driver and the graphics hardware. Next, the hardware call is forwarded to the graphics hardware via the virtual connection.
    Type: Application
    Filed: December 30, 2004
    Publication date: July 6, 2006
    Inventors: Hansong Zhang, David Shreiner
  • Publication number: 20060093044
    Abstract: A system and method for distributing data (e.g., imaging data such as pixels, or 3D graphics data such as points, lines, or polygons) from a single or a small number of data sources to a plurality of graphical processing units (graphics processors) for processing and display is presented. The system and method provide a pipelined and multithreaded approach that prioritizes movement of the data through a high-speed multiprocessor system (or a high-speed system of networked computers), according to the system topology. Multiple threads running on multiple processors in shared memory move the data from a storage device (e.g., a disk array), through the high-speed multiprocessor system, to graphics processor memory for display and optional processing through fragment programming. The data can also be moved in the reverse direction, back through the high-speed multiprocessor system, for storage on the disk array.
    Type: Application
    Filed: August 24, 2005
    Publication date: May 4, 2006
    Inventors: Brad Grantham, David Shreiner, Alan Commike