Abstract: An eFuse reference cell on a chip provides a reference voltage that is greater than a maximum voltage produced by an eFuse cell having an unblown eFuse on the chip but less than a minimum voltage produced by an eFuse cell having a blown eFuse on the chip. A reference current flows through a resistor and an unblown eFuse in the eFuse reference cell, producing the reference voltage. The reference voltage is used to create a mirrored copy of the reference current in the eFuse cell. The mirrored copy of the reference current flows through an eFuse in the eFuse cell. A comparator receives the reference voltage and the voltage produced by the eFuse cell. The comparator produces an output logic level responsive to the voltage produced by the eFuse cell compared to the reference voltage.

Abstract: An apparatus and method is disclosed for transmitting signals over a signal conductor using a precompensated driver that does not use a current source, and which drives the signal conductor with an impedance similar to the characteristic impedance of the signal conductor. Since no current source is used, the precompensated driver can operate at very low supply voltage.

Abstract: A method and apparatus are provided for implementing power control in multi-voltage input/output (I/O) circuits. First current biasing devices are provided for creating a first constant bias current. Second current biasing devices are provided for creating a second bias current. The second current biasing devices are activated at a first voltage and are deactivated at a second voltage. The first voltage is less than the second voltage.

Abstract: A dual mode, analog differential and complementary metal oxide semiconductor (CMOS) logic circuit is provided. The circuit includes a differential input for receiving a differential input signal. A switch pair is coupled to the differential input. A pair of load resistors coupled to the switch pair defines a differential output for providing a differential output signal. A current source is coupled to the switch pair. A control input receives a control signal and control circuitry coupled to the control input disable the current source to select a CMOS testing mode responsive to the control signal being activated.