Abstract: An device having an oscillator circuit modifiable between a first operating mode and a second operating mode, wherein the first operating mode has a first frequency accuracy and a first power consumption, wherein the second operating mode has a second frequency accuracy and a second power consumption, wherein the second frequency accuracy is more accurate than the first frequency accuracy and the second power consumption is higher than the first power consumption, and a control circuit in communication with the oscillator circuit to modify the operating mode of the oscillator circuit.

Abstract: An device having an oscillator circuit modifiable between a first operating mode and a second operating mode, wherein the first operating mode has a first frequency accuracy and a first power consumption, wherein the second operating mode has a second frequency accuracy and a second power consumption, wherein the second frequency accuracy is more accurate than the first frequency accuracy and the second power consumption is higher than the first power consumption, and a control circuit in communication with the oscillator circuit to modify the operating mode of the oscillator circuit.

Abstract: An integrated circuit includes a node coupled between a terminal of the integrated circuit and a transmitter circuit. The integrated circuit includes a switch circuit coupled between the node and a receiver circuit. The switch circuit includes a bias circuit coupled to the node. The bias circuit is configured to provide a first bias voltage to the node in response to an indication of a transmit mode of the terminal. The bias circuit is configured to provide a second bias voltage to the node in response to an indication of a receive mode of the terminal. The switch circuit may include a plurality of n-type devices coupled in series. Each of the plurality of n-type devices may include a triple-well, doubly-floating n-type device. The plurality of n-type devices may include a resistively-biased bulk terminal and a resistively-biased n-well.

Abstract: A mixed-voltage circuit employs a higher-voltage transistor in series connection with a lower-voltage transistor. To protect the lower-voltage transistor from transient overvoltage events, a series of one or more diodes is connected between the current terminals (i.e., the source and drain terminals) of the lower-voltage transistor so as to limit the voltage across the lower-voltage transistor. This diode protection mechanism also may be provided between the gate terminal and a current terminal of the lower-voltage transistor so as to protect against an overvoltage event at the gate of the lower-voltage transistor. In this manner, the mixed-voltage circuit can provide the performance benefits of mixed use of lower-voltage and higher-voltage transistors while reducing the risk of damaging the lower-voltage transistors due to the use of the higher-voltage power supply needed for operation of the mixed-voltage circuit.

Abstract: An apparatus includes a frequency mixer circuit configured to generate a baseband signal based on a local oscillator signal and a radio frequency signal. The apparatus includes a compensation circuit configured to generate a DC offset-compensated signal based on the baseband signal, a DC offset compensation signal, and a second signal. The DC offset compensation signal and the second signal have currents approximately equal in magnitude and opposite in direction. A current of the DC offset-compensated signal is substantially the same as a current of the baseband signal. The compensation circuit may include a DC digital-to-analog converter circuit configured to generate the DC offset compensation signal and the second signal based on a control signal.

Abstract: An integrated circuit includes a node coupled between a terminal of the integrated circuit and a transmitter circuit. The integrated circuit includes a switch circuit coupled between the node and a receiver circuit. The switch circuit includes a bias circuit coupled to the node. The bias circuit is configured to provide a first bias voltage to the node in response to an indication of a transmit mode of the terminal. The bias circuit is configured to provide a second bias voltage to the node in response to an indication of a receive mode of the terminal. The switch circuit may include a plurality of n-type devices coupled in series. Each of the plurality of n-type devices may include a triple-well, doubly-floating n-type device. The plurality of n-type devices may include a resistively-biased bulk terminal and a resistively-biased n-well.

Abstract: An apparatus includes a frequency mixer circuit configured to generate a baseband signal based on a local oscillator signal and a radio frequency signal. The apparatus includes a compensation circuit configured to generate a DC offset-compensated signal based on the baseband signal, a DC offset compensation signal, and a second signal. The DC offset compensation signal and the second signal have currents approximately equal in magnitude and opposite in direction. A current of the DC offset-compensated signal is substantially the same as a current of the baseband signal. The compensation circuit may include a DC digital-to-analog converter circuit configured to generate the DC offset compensation signal and the second signal based on a control signal.

Abstract: A mixed-voltage circuit employs a higher-voltage transistor in series connection with a lower-voltage transistor. To protect the lower-voltage transistor from transient overvoltage events, a series of one or more diodes is connected between the current terminals (i.e., the source and drain terminals) of the lower-voltage transistor so as to limit the voltage across the lower-voltage transistor. This diode protection mechanism also may be provided between the gate terminal and a current terminal of the lower-voltage transistor so as to protect against an overvoltage event at the gate of the lower-voltage transistor. In this manner, the mixed-voltage circuit can provide the performance benefits of mixed use of lower-voltage and higher-voltage transistors while reducing the risk of damaging the lower-voltage transistors due to the use of the higher-voltage power supply needed for operation of the mixed-voltage circuit.