Abstract: Described herein is a system comprising one or more external dynamic random access memory (DRAM) devices having a first programming unit buffer and a second programming unit buffer, an internal static RAM (SRAM) device, one or more non-volatile memory (NVM) devices, and a processing device, operatively coupled with the one or more external DRAM devices, the internal SRAM device, and the one or more NVM devices. The processing device transfers first write data from the first programming unit buffer to the internal SRAM device responsive to the first write data satisfying a programming unit (PU) threshold, the PU threshold pertaining to a PU of the one or more NVM devices. The processing device also writes the first write data from the internal SRAM device as a first programming unit to the one or more NVM devices, and transfers a second write data from the second programming unit buffer to the internal SRAM device responsive to the second write data satisfying the PU threshold.

Abstract: Described herein is a system comprising one or more external dynamic random access memory (DRAM) devices having a first programming unit buffer and a second programming unit buffer, an internal static RAM (SRAM) device, one or more non-volatile memory (NVM) devices, and a processing device, operatively coupled with the one or more external DRAM devices, the internal SRAM device, and the one or more NVM devices. The processing device transfers first write data from the first programming unit buffer to the internal SRAM device responsive to the first write data satisfying a programming unit (PU) threshold, the PU threshold pertaining to a PU of the one or more NVM devices. The processing device also writes the first write data from the internal SRAM device as a first programming unit to the one or more NVM devices, and transfers a second write data from the second programming unit buffer to the internal SRAM device responsive to the second write data satisfying the PU threshold.

Abstract: Described herein are embodiments related to a two-stage hybrid memory buffer for multiple streams in memory sub-systems. A processing device determines that first write data of a first stream stored in a host buffer component satisfies a threshold to program a first programming unit. The processing device transfers the first write data to the staging buffer component from the host buffer component, and writes the first write data from the staging buffer component as the first programming unit to a first die of multiple non-volatile memory (NVM) dies. The processing device determines that second write data of a second stream satisfies a threshold to program a second programming unit, transfers the second write data to the staging buffer component from the host buffer component, and writes the second write data from the staging buffer component as the second programming unit to a second die of the multiple NVM dies.

Abstract: Described herein are embodiments related to a two-stage hybrid memory buffer for multiple streams in memory sub-systems. A processing device determines that first write data of a first stream stored in a host buffer component satisfies a threshold to program a first programming unit. The processing device transfers the first write data to the staging buffer component from the host buffer component, and writes the first write data from the staging buffer component as the first programming unit to a first die of multiple non-volatile memory (NVM) dies. The processing device determines that second write data of a second stream satisfies a threshold to program a second programming unit, transfers the second write data to the staging buffer component from the host buffer component, and writes the second write data from the staging buffer component as the second programming unit to a second die of the multiple NVM dies.

Abstract: A method for discarding perpetually-rejected packets in a fabric-based interconnect having a reliable physical layer is disclosed. A transmitting component keeps a count of the number of negative acknowledgements (NAKs) it receives from the receiving component for packets the transmitting component sends. If the transmitting component receives a number of consecutive NAKs for the same packet that exceeds some pre-determined threshold, the packet is not resent, but is, instead, treated as having been acknowledged, and subsequent packets are allowed to be transmitted. Higher-level processes are then notified of the problem so as to allow the error to be dealt with at a higher level, but without obstructing the flow of packets on the physical layer.