Patents by Inventor David Sonnier

David Sonnier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8677075
    Abstract: Described embodiments provide a network processor having a plurality of processing modules coupled to a system cache and a shared memory. A memory manager allocates blocks of the shared memory to a requesting one of the processing modules. The allocated blocks store data corresponding to packets received by the network processor. The memory manager maintains a reference count for each allocated memory block indicating a number of processing modules accessing the block. One of the processing modules reads the data stored in the allocated memory blocks, stores the read data to corresponding entries of the system cache and operates on the data stored in the system cache. Upon completion of operation on the data, the processing module requests to decrement the reference count of each memory block. Based on the reference count, the memory manager invalidates the entries of the system cache and deallocates the memory blocks.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: March 18, 2014
    Assignee: LSI Corporation
    Inventors: Deepak Mital, William Burroughs, David Sonnier, Steven Pollock, David Brown, Joseph Hasting
  • Patent number: 8638805
    Abstract: Described embodiments provide for restructuring a scheduling hierarchy of a network processor having a plurality of processing modules and a shared memory. The scheduling hierarchy schedules packets for transmission. The network processor generates tasks corresponding to each received packet associated with a data flow. A traffic manager receives tasks provided by one of the processing modules and determines a queue of the scheduling hierarchy corresponding to the task. The queue has a parent scheduler at each of one or more next levels of the scheduling hierarchy up to a root scheduler, forming a branch of the hierarchy. The traffic manager determines if the queue and one or more of the parent schedulers of the branch should be restructured. If so, the traffic manager drops subsequently received tasks for the branch, drains all tasks of the branch, and removes the corresponding nodes of the branch from the scheduling hierarchy.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: January 28, 2014
    Assignee: LSI Corporation
    Inventors: Balakrishnan Sundararaman, Shashank Nemawarkar, David Sonnier, Shailendra Aulakh, Allen Vestal
  • Patent number: 8619787
    Abstract: Described embodiments provide for scheduling packets for transmission by a network processor. A traffic manager generates a tree scheduling hierarchy having a root scheduler and N scheduler levels. The network processor generates tasks corresponding to received packets. The traffic manager enqueues the received task in the associated queue, the queue having a corresponding parent scheduler at each of one or more next levels of the scheduling hierarchy up to the root scheduler. Each scheduler determines one or more tasks to schedule from a given queue based on a default packet size of the packet corresponding to the task. The corresponding packet data is read from a shared memory, and, at each corresponding parent scheduler up to the root scheduler, an actual size of the packet data is updated. Scheduling weights of each corresponding parent scheduler are updated based on the actual size of the packet data.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: December 31, 2013
    Assignee: LSI Corporation
    Inventors: David Sonnier, Balakrishnan Sundararaman
  • Patent number: 8615013
    Abstract: Described embodiments provide rate setting for nodes of a scheduling hierarchy of a network processor. The scheduling hierarchy is a tree structure having a root scheduler and N scheduler levels. The network processor generates tasks corresponding to received packets. A traffic manager queues received tasks in a queue of the scheduling hierarchy associated with a data flow of the task. The queue has a parent scheduler at each level of the hierarchy up to the root scheduler. A scheduler selects a child node for transmission based on a number of arbitration credits in an arbitration credit bucket of each child. An arbitration credit value is determined for each child by maintaining a time stamp value corresponding to a time value of a previous selection of the child node and determining an elapsed time value based on the time stamp value and a current time value, scaled by a scaling factor.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: December 24, 2013
    Assignee: Agere Systems LLC
    Inventors: David Sonnier, Balakrishnan Sundararaman
  • Patent number: 8576862
    Abstract: Described embodiments provide for arbitrating between nodes of scheduling hierarchy of a network processor. A traffic manager generates a tree scheduling hierarchy having a root scheduler and N scheduler levels. The network processor generates tasks corresponding to received packets. The traffic manager queues the received task in an associated queue of the scheduling hierarchy. The root scheduler performs smooth deficit weighted round robin (SDWRR) arbitration between each child node of the root scheduler. The SDWRR arbitration includes checking one or more status indicators of each child node of the given scheduler and selecting, based on the status indicators, a first active child node of the scheduler and updating the one or more status indicators corresponding to the selected child node. Thus, a task is scheduled for transmission by the traffic manager every cycle of the network processor.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: November 5, 2013
    Assignee: LSI Corporation
    Inventors: David Sonnier, Balakrishnan Sundararaman, Shashank Nemawarkar
  • Patent number: 8565250
    Abstract: Described embodiments schedule packets for transmission by a network processor. A traffic manager generates a scheduling hierarchy having a root scheduler and N levels. The network processor generates tasks corresponding to received packets. The traffic manager enqueues tasks in an associated queue. The queue has a corresponding level M, with a corresponding parent scheduler at each of M?1 levels in the scheduling hierarchy, where M is less than or equal to N. In a single scheduling cycle, a parent scheduler selects a child node to transmit one or more tasks, and the child node responds whether the scheduling is accepted, and if so, with a number of tasks for scheduling. Starting at the parent scheduler and iteratively repeating at each level until reaching the root scheduler, statistics corresponding to the selected node are updated. Output packets corresponding to the scheduled tasks are transmitted, thereby achieving a superscalar task scheduling throughput.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: October 22, 2013
    Assignee: LSI Corporation
    Inventors: Shashank Nemawarkar, Balakrishnan Sundararaman, David Sonnier
  • Publication number: 20120131283
    Abstract: Described embodiments provide a network processor having a plurality of processing modules coupled to a system cache and a shared memory. A memory manager allocates blocks of the shared memory to a requesting one of the processing modules. The allocated blocks store data corresponding to packets received by the network processor. The memory manager maintains a reference count for each allocated memory block indicating a number of processing modules accessing the block. One of the processing modules reads the data stored in the allocated memory blocks, stores the read data to corresponding entries of the system cache and operates on the data stored in the system cache. Upon completion of operation on the data, the processing module requests to decrement the reference count of each memory block. Based on the reference count, the memory manager invalidates the entries of the system cache and deallocates the memory blocks.
    Type: Application
    Filed: January 27, 2012
    Publication date: May 24, 2012
    Inventors: Deepak Mital, William Burroughs, David Sonnier, Steven Pollock, David Brown, Joseph Hasting
  • Publication number: 20120084498
    Abstract: Described embodiments provide a method of controlling processing flow in a network processor having one or more processing modules. A given one of the processing modules loads a script into a compute engine. The script includes instructions for the compute engine. The given one of the processing modules loads a register file into the compute engine. The register file includes operands for the instructions of the loaded script. A tracking vector of the compute engine is initialized to a default value, and the compute engine executes the instructions of the loaded script based on the operands of the loaded register file. The compute engine updates corresponding portions of the register file with updated data corresponding to the executed script. The tracking vector tracks the updated portions of the register file. The compute engine provides the tracking vector and the updated register file to the given one of the processing modules.
    Type: Application
    Filed: December 9, 2011
    Publication date: April 5, 2012
    Inventors: David Sonnier, Chris Randall Stone, Charles Edwards Peet, JR.
  • Publication number: 20120020371
    Abstract: Described embodiments schedule packets for transmission by a network processor. A traffic manager generates a scheduling hierarchy having a root scheduler and N levels. The network processor generates tasks corresponding to received packets. The traffic manager enqueues tasks in an associated queue. The queue has a corresponding level M, with a corresponding parent scheduler at each of M?1 levels in the scheduling hierarchy, where M is less than or equal to N. In a single scheduling cycle, a parent scheduler selects a child node to transmit one or more tasks, and the child node responds whether the scheduling is accepted, and if so, with a number of tasks for scheduling. Starting at the parent scheduler and iteratively repeating at each level until reaching the root scheduler, statistics corresponding to the selected node are updated. Output packets corresponding to the scheduled tasks are transmitted, thereby achieving a superscalar task scheduling throughput.
    Type: Application
    Filed: September 30, 2011
    Publication date: January 26, 2012
    Inventors: Shashank Nemawarkar, Balakrishnan Sundararaman, David Sonnier
  • Publication number: 20120020249
    Abstract: Described embodiments provide for controlling a state of each node in a scheduling hierarchy of a network processor. A traffic manager generates a tree scheduling hierarchy having a root scheduler and N scheduler levels. The network processor generates tasks corresponding to received packets. A traffic manager enqueues received tasks in a queue of the scheduling hierarchy associated with a data flow. The traffic manager maintains scheduling data structures for each node in the scheduling hierarchy. The scheduling data structures include a backpressure indicator and a timer indicator. If the backpressure indicator is set, the traffic manager sets the node as unavailable for scheduling and removes the node from the scheduling hierarchy. If the timer indicator is set, the traffic managers sets the node as unavailable for scheduling. Otherwise, if neither the backpressure indicator nor the timer indicator is set, the traffic manager sets the node as available for scheduling.
    Type: Application
    Filed: September 30, 2011
    Publication date: January 26, 2012
    Inventors: Balakrishnan Sundararaman, Shashank Nemawarkar, David Sonnier, Shailendra Aulakh
  • Publication number: 20120020369
    Abstract: Described embodiments provide for dynamically constructing a scheduling hierarchy of a network processor. A traffic manager generates a tree scheduling hierarchy having a root scheduler and N scheduler levels. The network processor generates tasks corresponding to received packets. The traffic manager queues the received task in the associated queue, the queue having a corresponding parent scheduler at each of one or more next levels of the scheduling hierarchy up to the root scheduler. A parent scheduler selects, starting at the root scheduler and iteratively repeating at each of the corresponding N scheduling levels until a queue is selected, a child node to transmit at least one task. The traffic manager forms output packets for transmission based on the at least one task from the selected queue.
    Type: Application
    Filed: September 30, 2011
    Publication date: January 26, 2012
    Inventors: Balakrishnan Sundararaman, Shashank Nemawarkar, David Sonnier, Shailendra Aulakh
  • Publication number: 20120020370
    Abstract: Described embodiments provide for arbitrating between nodes of scheduling hierarchy of a network processor. A traffic manager generates a tree scheduling hierarchy having a root scheduler and N scheduler levels. The network processor generates tasks corresponding to received packets. The traffic manager queues the received task in an associated queue of the scheduling hierarchy. The root scheduler performs smooth deficit weighted round robin (SDWRR) arbitration between each child node of the root scheduler. The SDWRR arbitration includes checking one or more status indicators of each child node of the given scheduler and selecting, based on the status indicators, a first active child node of the scheduler and updating the one or more status indicators corresponding to the selected child node. Thus, a task is scheduled for transmission by the traffic manager every cycle of the network processor.
    Type: Application
    Filed: September 30, 2011
    Publication date: January 26, 2012
    Inventors: David Sonnier, Balakrishnan Sundararaman, Shashank Nemawarkar
  • Publication number: 20120023498
    Abstract: Described embodiments provide for queuing tasks in a scheduling hierarchy of a network processor. A traffic manager generates a tree scheduling hierarchy having a root scheduler and N scheduler levels. The network processor generates tasks corresponding to received packets. The traffic manager performs a task enqueue operation for the task. The task enqueue operation includes adding the received task to an associated queue of the scheduling hierarchy, where the queue is associated with a data flow of the received task. The queue has a corresponding scheduler level M, where M is a positive integer less than or equal to N. Starting at the queue and iteratively repeating at each scheduling level until reaching the root scheduler, each node in the scheduling hierarchy maintains an actual count of tasks corresponding to the node. Each node communicates a capped task count to a corresponding parent scheduler at a relative next scheduler level.
    Type: Application
    Filed: September 30, 2011
    Publication date: January 26, 2012
    Inventors: Balakrishnan Sundararaman, Shashank Nemawarkar, David Sonnier, Allen Vestal
  • Publication number: 20120020368
    Abstract: Described embodiments provide for dynamically controlling a scheduling rate of each node in a scheduling hierarchy of a network processor. A traffic manager generates a tree scheduling hierarchy having a root scheduler and N scheduler levels. The network processor generates tasks corresponding to received packets. A traffic manager enqueues received tasks in a queue of the scheduling hierarchy associated with a data flow. The queue has a parent scheduler at each level of the hierarchy up to the root scheduler. The traffic manager maintains one or more scheduling data structures for each node in the scheduling hierarchy. If the traffic manager receives a rate reduction request corresponding to a given node of the scheduling hierarchy, the traffic manager updates one or more indicators in the scheduling data structure corresponding to the given node and removes the given node from the scheduling hierarchy, thereby reducing the scheduling rate of the node.
    Type: Application
    Filed: September 30, 2011
    Publication date: January 26, 2012
    Inventors: Balakrishnan Sundararaman, Shashank Nemawarkar, David Sonnier, Allen Vestal
  • Publication number: 20120020210
    Abstract: Described embodiments provide for scheduling packets for transmission by a network processor. A traffic manager generates a tree scheduling hierarchy having a root scheduler and N scheduler levels. The network processor generates tasks corresponding to received packets. The traffic manager enqueues the received task in the associated queue, the queue having a corresponding parent scheduler at each of one or more next levels of the scheduling hierarchy up to the root scheduler. Each scheduler determines one or more tasks to schedule from a given queue based on a default packet size of the packet corresponding to the task. The corresponding packet data is read from a shared memory, and, at each corresponding parent scheduler up to the root scheduler, an actual size of the packet data is updated. Scheduling weights of each corresponding parent scheduler are updated based on the actual size of the packet data.
    Type: Application
    Filed: September 30, 2011
    Publication date: January 26, 2012
    Inventors: David Sonnier, Balakrishnan Sundararaman
  • Publication number: 20120020250
    Abstract: Described embodiments provide sharing data between nodes in a scheduling hierarchy of a network processor. A traffic manager generates a tree scheduling hierarchy having a root scheduler and N scheduler levels. The network processor generates tasks corresponding to received packets, each task having a shared parameter ID. The traffic manager determines the shared parameter ID value of the received task and queues the received task in a queue of the scheduling hierarchy. The queue has a scheduler level M and a parent scheduler at each of M-1 levels in the scheduling hierarchy. The traffic manager determines a shared parameter ID value of the queue. The traffic manager loads, from a shared memory to a corresponding level one cache, one or more shared parameter values corresponding to at least one of the determined shared parameter ID value of the received task and the determined shared parameter ID value of the queue.
    Type: Application
    Filed: September 30, 2011
    Publication date: January 26, 2012
    Inventors: Balakrishnan Sundararaman, Shailendra Aulakh, David Sonnier, Shashank Nemawarkar
  • Publication number: 20120020223
    Abstract: Described embodiments provide rate setting for nodes of a scheduling hierarchy of a network processor. The scheduling hierarchy is a tree structure having a root scheduler and N scheduler levels. The network processor generates tasks corresponding to received packets. A traffic manager queues received tasks in a queue of the scheduling hierarchy associated with a data flow of the task. The queue has a parent scheduler at each level of the hierarchy up to the root scheduler. A scheduler selects a child node for transmission based on a number of arbitration credits in an arbitration credit bucket of each child. An arbitration credit value is determined for each child by maintaining a time stamp value corresponding to a time value of a previous selection of the child node and determining an elapsed time value based on the time stamp value and a current time value, scaled by a scaling factor.
    Type: Application
    Filed: September 30, 2011
    Publication date: January 26, 2012
    Inventors: David Sonnier, Balakrishnan Sundararaman
  • Publication number: 20120020366
    Abstract: Described embodiments provide for restructuring a scheduling hierarchy of a network processor having a plurality of processing modules and a shared memory. The scheduling hierarchy schedules packets for transmission. The network processor generates tasks corresponding to each received packet associated with a data flow. A traffic manager receives tasks provided by one of the processing modules and determines a queue of the scheduling hierarchy corresponding to the task. The queue has a parent scheduler at each of one or more next levels of the scheduling hierarchy up to a root scheduler, forming a branch of the hierarchy. The traffic manager determines if the queue and one or more of the parent schedulers of the branch should be restructured. If so, the traffic manager drops subsequently received tasks for the branch, drains all tasks of the branch, and removes the corresponding nodes of the branch from the scheduling hierarchy.
    Type: Application
    Filed: September 30, 2011
    Publication date: January 26, 2012
    Inventors: Balakrishnan Sundararaman, Shashank Nemawarkar, David Sonnier, Shailendra Aulakh, Allen Vestal
  • Publication number: 20070276850
    Abstract: Improved techniques are disclosed for performing an in-service upgrade of software associated with a network or packet processor. By way of example, a method of managing data structures associated with code executable on a packet processor includes the following steps. Data structures in the code are identified as being one of static data structures and non-static data structures, wherein a static data structure includes a data structure that is not changed during execution of the packet processor code and a non-static data structure includes a data structure that is changed during execution of the packet processor code. One or more data structures associated with the packet processor code are managed in a manner specific to the identification of the one or more data structures as static data structures or non-static data structures. At least a portion of the data structures may include tree structures.
    Type: Application
    Filed: April 27, 2006
    Publication date: November 29, 2007
    Inventors: Rajarshi Bhattacharya, David Sonnier, Narender Vangati
  • Publication number: 20070253451
    Abstract: Improved timeout table mechanism are disclosed. By way of example, a method for providing timeout delays for data queues in a processing system includes the following steps. A timeout structure is maintained. The timeout structure includes two or more groups, each group including two or more bins, each bin having a range of timeout delay values associated therewith, each group having a weight associated therewith, the weight of each group being based on a rate and a quantity of queues assignable to each group. A timeout delay value to be assigned to a data queue in the processing system is selected.
    Type: Application
    Filed: April 27, 2006
    Publication date: November 1, 2007
    Inventors: Christopher Koob, Ali Poursepanj, David Sonnier