Patents by Inventor David Sotta

David Sotta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11876073
    Abstract: A process for collectively fabricating a plurality of semiconductor structures comprises providing a substrate including a carrier having a main face, a dielectric layer on the main face of the carrier and a plurality of crystalline semiconductor growth islands on the dielectric layer. At least one crystalline semiconductor active layer is formed on the growth islands. After the step of forming the active layer, trenches are formed in the active layer and in the growth islands in order to define the plurality of semiconductor structures.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: January 16, 2024
    Assignee: SOITEC
    Inventor: David Sotta
  • Patent number: 11735685
    Abstract: A method for preparing a crystalline semiconductor layer in order for the layer to be provided with a specific lattice parameter involves a relaxation procedure that is applied for a first time to a first start donor substrate in order to obtain a second donor substrate. Using the second donor substrate as the start donor substrate, the relaxation procedure is repeated for a number of times that is sufficient for the lattice parameter of the relaxed layer to be provided with the specific lattice parameter. A set of substrates may be obtained by the method.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: August 22, 2023
    Assignee: Soitec
    Inventor: David Sotta
  • Publication number: 20220140190
    Abstract: An optoelectronic semiconductor structure comprises an InGaN-based active layer disposed between an n-type injection layer and a p-type injection layer, the p-type injection layer comprising a first InGaN layer having a thickness between 50 and 350 nm and, disposed on the first layer, a second layer having a GaN surface portion.
    Type: Application
    Filed: February 25, 2020
    Publication date: May 5, 2022
    Inventors: David Sotta, Mariia Rozhavskaia, Benjamin Daminlano
  • Patent number: 11295950
    Abstract: A structure that can be used to manufacture at least one active layer made of a III-V material thereon includes a substrate comprising a carrier having a main face, a dielectric layer located on the main face of the carrier, and a plurality of single-crystal semiconductor islands located directly on the dielectric layer. The islands have an upper surface in order to serve as a seed surface for the growth of the active layer. The structure further comprises a seed layer located between the single-crystal semiconductor islands, directly on the portion of the dielectric layer that is not covered by the islands, without masking the upper surface of the islands, so that the dielectric layer is not exposed to the external environment.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: April 5, 2022
    Assignee: Soitec
    Inventors: David Sotta, Jean-Marc Bethoux, Oleg Kononchuk
  • Patent number: 11245050
    Abstract: A method for preparing a crystalline semiconductor layer in order for the layer to be provided with a specific lattice parameter involves a relaxation procedure that is applied for a first time to a first start donor substrate in order to obtain a second donor substrate. Using the second donor substrate as the start donor substrate, the relaxation procedure is repeated for a number of times that is sufficient for the lattice parameter of the relaxed layer to be provided with the specific lattice parameter. A set of substrates may be obtained by the method.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: February 8, 2022
    Assignee: Soitec
    Inventor: David Sotta
  • Publication number: 20220005785
    Abstract: A process for collectively fabricating a plurality of semiconductor structures comprises providing a substrate including a carrier having a main face, a dielectric layer on the main face of the carrier and a plurality of crystalline semiconductor growth islands on the dielectric layer. At least one crystalline semiconductor active layer is formed on the growth islands. After the step of forming the active layer, trenches are formed in the active layer and in the growth islands in order to define the plurality of semiconductor structures.
    Type: Application
    Filed: October 24, 2019
    Publication date: January 6, 2022
    Inventor: David Sotta
  • Publication number: 20210351318
    Abstract: A method for preparing a crystalline semiconductor layer in order for the layer to be provided with a specific lattice parameter involves a relaxation procedure that is applied for a first time to a first start donor substrate in order to obtain a second donor substrate. Using the second donor substrate as the start donor substrate, the relaxation procedure is repeated for a number of times that is sufficient for the lattice parameter of the relaxed layer to be provided with the specific lattice parameter. A set of substrates may be obtained by the method.
    Type: Application
    Filed: July 26, 2021
    Publication date: November 11, 2021
    Inventor: David Sotta
  • Publication number: 20210210653
    Abstract: A growth substrate for forming optoelectronic devices comprises a growth medium and, arranged on the growth medium, a first group of crystalline semiconductor islands having a first lattice parameter and a second group of crystalline semiconductor islands having a second lattice parameter that is different from the first. Methods may be used to manufacture such growth substrates. The methods may be used to provide a monolithic micro-panel or light-emitting diodes or a micro-display screen.
    Type: Application
    Filed: March 14, 2018
    Publication date: July 8, 2021
    Inventors: David Sotta, Olivier Ledoux, Olivier Bonnin, Jean-Marc Bethoux, Morgane Logiou, RaphaƩl Caulmilone
  • Publication number: 20200013921
    Abstract: A method for preparing a crystalline semiconductor layer in order for the layer to be provided with a specific lattice parameter involves a relaxation procedure that is applied for a first time to a first start donor substrate in order to obtain a second donor substrate. Using the second donor substrate as the start donor substrate, the relaxation procedure is repeated for a number of times that is sufficient for the lattice parameter of the relaxed layer to be provided with the specific lattice parameter. A set of substrates may be obtained by the method.
    Type: Application
    Filed: February 26, 2018
    Publication date: January 9, 2020
    Applicant: Soitec
    Inventor: David Sotta
  • Publication number: 20190228967
    Abstract: A structure that can be used to manufacture at least one active layer made of a III-V material thereon includes a substrate comprising a carrier having a main face, a dielectric layer located on the main face of the carrier, and a plurality of single-crystal semiconductor islands located directly on the dielectric layer. The islands have an upper surface in order to serve as a seed surface for the growth of the active layer. The structure further comprises a seed layer located between the single-crystal semiconductor islands, directly on the portion of the dielectric layer that is not covered by the islands, without masking the upper surface of the islands, so that the dielectric layer is not exposed to the external environment.
    Type: Application
    Filed: September 21, 2017
    Publication date: July 25, 2019
    Inventors: David Sotta, Jean-Marc Bethoux, Oleg Kononchuk
  • Patent number: 10084011
    Abstract: A method for manufacturing a plurality of crystalline semiconductor islands having a variety of lattice parameters comprises providing a substrate including a medium, a flow layer disposed on the medium, and a plurality of strained crystalline semiconductor islands having an initial lattice parameter arranged on the flow layer. The strained semiconductor islands are selectively treated so as to form a first group of strained islands having a first lateral expansion potential, and a second group of strained islands having a second lateral expansion potential that is different from the first lateral expansion potential. The substrate is heat treated at a temperature at or above a glass transition temperature of the flow layer to cause differentiated relaxation of the islands of the first and second groups, such that a lattice parameter of the first group of relaxed islands differs from a lattice parameter of the second group of relaxed islands.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: September 25, 2018
    Assignee: Soitec
    Inventors: David Sotta, Olivier Ledoux, Olivier Bonnin
  • Publication number: 20180269253
    Abstract: A method for manufacturing a plurality of crystalline semiconductor islands having a variety of lattice parameters comprises providing a substrate including a medium, a flow layer disposed on the medium, and a plurality of strained crystalline semiconductor islands having an initial lattice parameter arranged on the flow layer. The strained semiconductor islands are selectively treated so as to form a first group of strained islands having a first lateral expansion potential, and a second group of strained islands having a second lateral expansion potential that is different from the first lateral expansion potential. The substrate is heat treated at a temperature at or above a glass transition temperature of the flow layer to cause differentiated relaxation of the islands of the first and second groups, such that a lattice parameter of the first group of relaxed islands differs from a lattice parameter of the second group of relaxed islands.
    Type: Application
    Filed: April 19, 2017
    Publication date: September 20, 2018
    Inventors: David Sotta, Olivier Ledoux, Olivier Bonnin
  • Publication number: 20120199956
    Abstract: The present invention relates to process for recycling a source substrate that has a surface region and regions in relief on the surface region, with the regions in relief corresponding to residual regions of a layer of the source substrate that were not being separated from the rest of the source substrate during a prior removal step. The process includes selective electromagnetic irradiation of the source substrate at a wavelength such that the damaged material of the surface region absorbs the electromagnetic irradiation. The present invention also relates to a recycled source substrate and to a process for transferring a layer from a source substrate recycled for this purpose.
    Type: Application
    Filed: February 7, 2012
    Publication date: August 9, 2012
    Inventors: Monique Lecomte, Pascal Guenard, Sophie Rigal, David Sotta, Fabienne Janin, Christelle Veytizou