Abstract: A compressor assembly comprising first and second housing structures connected to one another. A compression chamber is formed integrally within the first and second housing structures. A separation chamber is formed integrally within the first and second housing structures. An internal fluid passage extends between the compression chamber and the separation chamber.

Abstract: A single chip embedded microcontroller has a processor that communicates with multiple non-volatile erasable PROMS which may be an OTPROM and an EEPROM. The processor also communicates with a high voltage generator that produces the erase and write voltages for the OTPROM and EEPROM. A switch communicates with the high voltage generator and switches the erase and write voltages alternately between the OTPROM and EEPROM. The OTPROM and EEPROM are FLASH arrays. The FLASH array technology allows the EEPROM and OTPROM to have similar erase and write voltages and therefore to share one high voltage generator. The high voltage generator is switched alternately between the first and second non-volatile erasable PROM arrays to enforce the principle that the EEPROM and OTPROM cannot be written to or erased at the same and may only be written to or erased one at a time.

Abstract: An emulated EEPROM memory array is disclosed based on non-volatile floating gate memory cells, such as Flash cells, where a small group of bits share a common source line and common row lines, so that the small group of bits may be treated as a group during program and erase modes to control the issues of program disturb and effective endurance. The bits common to the shared source line make up the emulated EEPROM page which is the smallest unit that can be erased and reprogrammed, without disturbing other bits. The memory array is physically divided up into groups of columns. One embodiment employs four memory arrays, each consisting of 32 columns and 512 page rows (all four arrays providing a total of 1024 pages with each page having 8 bytes or 64 bits). A global row decoder decodes the major rows and a page row driver and a page source driver enable the individual rows and sources that make up a given array.

Abstract: An emulated EEPROM memory array is disclosed based on non-volatile floating gate memory cells, such as Flash cells, where a small group of bits share a common source line and common row lines, so that the small group of bits may be treated as a group during program and erase modes to control the issues of program disturb and effective endurance. The bits common to the shared source line make up the emulated EEPROM page which is the smallest unit that can be erased and reprogrammed, without disturbing other bits. The memory array is physically divided up into groups of columns. One embodiment employs four memory arrays, each consisting of 32 columns and 512 page rows (all four arrays providing a total of 1024 pages with each page having 8 bytes or 64 bits). A global row decoder decodes the major rows and a page row driver and a page source driver enable the individual rows and sources that make up a given array.

Abstract: A single chip embedded microcontroller has a processor that communicates with multiple non-volatile erasable PROMS which may be an OTPROM and an EEPROM. The processor also communicates with a high voltage generator that produces the erase and write voltages for the OTPROM and EEPROM. A switch communicates with the high voltage generator and switches the erase and write voltages alternately between the OTPROM and EEPROM. The OTPROM and EEPROM are FLASH arrays. The FLASH array technology allows the EEPROM and OTPROM to have similar erase and write voltages and therefore to share one high voltage generator. The high voltage generator is switched alternately between the first and second non-volatile erasable PROM arrays to enforce the principle that the EEPROM and OTPROM cannot be written to or erased at the same and may only be written to or erased one at a time.

Abstract: An air compressor assembly of the rotary screw type. The air compressor assembly comprises a housing having an inlet end and a discharge end. An internal working chamber extends within the housing and terminates in a discharge end face at the discharge end of the housing. At least one rotor is mounted for rotation and axial movement within the working chamber. The rotor has a discharge end surface having a step defined thereon. A thrust piston extends from the rotor and is positioned within a thrust piston chamber. A pressure source is associated with the thrust piston chamber and is controllable between a high pressure condition and a reduced pressure condition to control the position of the rotor relative to the discharge end face. A method of mounting a rotor with a desired end clearance is also provided.

Abstract: By reducing the size of the blocks or pages that are contained in a FLASH EEPROM array that must be erased in a write or erase operation, the size of register needed is reduced, making it easier for the processor to handle smaller blocks of information, reducing the size and complexity of the microprocessor, and increasing the endurance of the FLASH EEPROM allowing it to be used in place of the state of the art EEPROM. Replacing mask ROM by flash EEPROM allows full testing of the code storage area as well as allowing customers to use that space for testing in their manufacturing procedures. The code used for testing can then be cleared and reprogrammed with the final code storage before final shipment.

Abstract: A logic level detection circuit that includes a sense amplifier and a consumption equilibration circuit that is topologically distinct from the sense amplifier and that reduces and/or substantially eliminates data dependent electrical consumption by having a data dependent electrical consumption that compensates the data dependent electrical consumption of the sense amplifier. The sense amplifier may be implemented as a current-sensing sense amplifier, and the consumption equilibration circuit may be implemented as a selectively enabled current source that is responsive to a signal generated by the current-sensing sense amplifier. The consumption equilibration circuit may be implemented with a small number of transistors and in a small chip area compared to the number of transistors and chip area used for implementing the sense amplifier.

Abstract: By reducing the size of the blocks or pages that are contained in a FLASH EEPROM array that must be erased in a write or erase operation, the size of register needed is reduced, making it easier for the processor to handle smaller blocks of information, reducing the size and complexity of the microprocessor, and increasing the endurance of the FLASH EEPROM allowing it to be used in place of the state of the art EEPROM. Replacing mask ROM by flash EEPROM allows full testing of the code storage area as well as allowing customers to use that space for testing in their manufacturing procedures. The code used for testing can then be cleared and reprogrammed with the final code storage before final shipment.

Abstract: By reducing the size of the blocks or pages that are contained in a FLASH EEPROM array that must be erased in a write or erase operation, the size of register needed is reduced, making it easier for the processor to handle smaller blocks of information, reducing the size and complexity of the microprocessor, and increasing the endurance of the FLASH EEPROM allowing it to be used in place of the state of the art EEPROM. Replacing mask ROM by flash EEPROM allows full testing of the code storage area as well as allowing customers to use that space for testing in their manufacturing procedures. The code used for testing can then be cleared and reprogrammed with the final code storage before final shipment.

Abstract: A logic level detection circuit that includes a sense amplifier and a consumption equilibration circuit that is topologically distinct from the sense amplifier and that reduces and/or substantially eliminates data dependent electrical consumption by having a data dependent electrical consumption that compensates the data dependent electrical consumption of the sense amplifier. The sense amplifier may be implemented as a current-sensing sense amplifier, and the consumption equilibration circuit may be implemented as a selectively enabled current source that is responsive to a signal generated by the current-sensing sense amplifier. The consumption equilibration circuit may be implemented with a small number of transistors and in a small chip area compared to the number of transistors and chip area used for implementing the sense amplifier.

Abstract: A logic level detection circuit that includes a sense amplifier and a consumption equilibration circuit that is topologically distinct from the sense amplifier and that reduces and/or substantially eliminates data dependent electrical consumption by having a data dependent electrical consumption that compensates the data dependent electrical consumption of the sense amplifier. The sense amplifier may be implemented as a current-sensing sense amplifier, and the consumption equilibration circuit may be implemented as a selectively enabled current source that is responsive to a signal generated by the current-sensing sense amplifier. The consumption equilibration circuit may be implemented with a small number of transistors and in a small chip area compared to the number of transistors and chip area used for implementing the sense amplifier.

Abstract: The present invention discloses a circuit for controlling operation of a functional circuit in a device based on a test result during testing. The circuit comprises a first storage element configured to be in one of a first state and a second state according to the test result, and a first sensing element coupled to the first storage element for generating a first signal used to control the operation of the functional circuit.

Abstract: Method and apparatus for adjustment and control of an iterative method of recording analog signals with on-chip trimming techniques for later playback. The invention allows setting of various parameters for the multi iterative programming technique after chip fabrication so as to allow tighter control and thus higher resolution analog signal sample storage in a given or minimum amount of time. Such parameters include, but are not limited to: the step down voltage from the coarse programming cycle to the fine programming cycle, the incremental voltage increase between each fine pulse, the pulse width of each fine pulse, the number of fine pulses, the incremental voltage increase between each coarse pulse, the pulse width of each course pulse, the number of coarse pulses, and the offset, VOS, which stops further coarse pulses and holds the last coarse level as a reference for the following fine cycle.

Abstract: A washing machine including a pump which selectively passes washing liquid to a filter or to a drain, the pump having a vaned impeller driven by an impeller shaft, the impeller structure being provided with a collar in circumscribing relation to the shaft, and a pump housing having a tubular portion in closely spaced relation to the periphery of the collar, the tubular portion having a serrated portion cooperating with the collar to shred lint delivered to the space between the collar and the serrated portion.