Abstract: A method for determining overlay measurements includes orienting a wafer to align portions of lines of a pattern of an overlay mark with a direction in which a source emits light at the wafer and align other portions of the lines of the pattern to extend in a direction perpendicular to the direction in which the illumination source emits light at the wafer. The method includes capturing at least one image of the wafer via an imager sensor. The method also includes determining contrasts of regions of the overlay mark and determining a location of the overlay mark. Overlay marks include a pattern defining an array of columns. Each column includes a set of continuous lines oriented parallel to each other and extending in a first direction within a first region of a column and extending in a second different direction in a second region of the column.

Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an electrically insulative material at least partially over a first electrically conductive feature and a second electrically conductive feature. The method can further include forming a ring of electrically conductive material around a sidewall of the insulative material defining the opening, wherein the ring of electrically conductive material includes (a) a first via portion over the first electrically conductive feature, (b) a second via portion over the second electrically conductive feature, and (c) connecting portions extending between the first and second via portions. Finally, the method can include removing the connecting portions of the ring of electrically conductive material to electrically isolate the first via portion from the second via portion.

Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an insulative material at least partially over an electrically conductive feature. The method can further include forming a ring of electrically non-conductive material extending at least partially about a sidewall of the insulative material that defines the opening. The method can further include removing a portion of the ring to form an opening over the electrically conductive feature, and then depositing an electrically conductive material into the opening in the ring to form a conductive via electrically coupled to the electrically conductive feature.

Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an electrically insulative material at least partially over a first electrically conductive feature and a second electrically conductive feature. The method can further include forming a ring of electrically conductive material around a sidewall of the insulative material defining the opening, wherein the ring of electrically conductive material includes (a) a first via portion over the first electrically conductive feature, (b) a second via portion over the second electrically conductive feature, and (c) connecting portions extending between the first and second via portions. Finally, the method can include removing the connecting portions of the ring of electrically conductive material to electrically isolate the first via portion from the second via portion.

Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an insulative material at least partially over an electrically conductive feature. The method can further include forming a ring of electrically non-conductive material extending at least partially about a sidewall of the insulative material that defines the opening. The method can further include removing a portion of the ring to form an opening over the electrically conductive feature, and then depositing an electrically conductive material into the opening in the ring to form a conductive via electrically coupled to the electrically conductive feature.

Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an electrically insulative material at least partially over a first electrically conductive feature and a second electrically conductive feature. The method can further include forming a ring of electrically conductive material around a sidewall of the insulative material defining the opening, wherein the ring of electrically conductive material includes (a) a first via portion over the first electrically conductive feature, (b) a second via portion over the second electrically conductive feature, and (c) connecting portions extending between the first and second via portions. Finally, the method can include removing the connecting portions of the ring of electrically conductive material to electrically isolate the first via portion from the second via portion.

Abstract: A method for determining overlay measurements includes orienting a wafer to align portions of lines of a pattern of an overlay mark with a direction in which a source emits light at the wafer and align other portions of the lines of the pattern to extend in a direction perpendicular to the direction in which the illumination source emits light at the wafer. The method includes capturing at least one image of the wafer via an imager sensor. The method also includes determining contrasts of regions of the overlay mark and determining a location of the overlay mark. Overlay marks include a pattern defining an array of columns. Each column includes a set of continuous lines oriented parallel to each other and extending in a first direction within a first region of a column and extending in a second different direction in a second region of the column.

Abstract: A method and apparatus are provided to in one aspect update data on a wireless mobile device. Available updates may include both mandatory and discretionary updates, where the mandatory updates are always installed on the wireless mobile device. In another aspect, a method and apparatus for of remotely instructing a wireless mobile device to perform a service is provided. The wireless mobile device receives a ping message that instructs it to retrieve further instruction for performing services actions on the wireless mobile device.

Abstract: A method and apparatus are provided to in one aspect update data on a wireless mobile device. Available updates may include both mandatory and discretionary updates, where the mandatory updates are always installed on the wireless mobile device. In another aspect, a method and apparatus for of remotely instructing a wireless mobile device to perform a service is provided. The wireless mobile device receives a ping message that instructs it to retrieve further instruction for performing services actions on the wireless mobile device.

Abstract: Pass-through interconnect structures for microelectronic dies and associated systems and methods are disclosed herein. In one embodiment, a microelectronic die assembly includes a support substrate, a first microelectronic die positioned at least partially over the support substrate, and a second microelectronic die positioned at least partially over the first die. The first die includes a semiconductor substrate, a conductive trace extending over a portion of the semiconductor substrate, a substrate pad between the trace and the portion of the semiconductor substrate, and a through-silicon via (TSV) extending through the trace, the substrate pad, and the portion of the semiconductor substrate. The second die is electrically coupled to the support substrate via a conductive path that includes the TSV.

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices. One example of a method of fabricating a semiconductor device comprises forming a conductive feature extending through a semiconductor substrate such that the conductive feature has a first end and a second end opposite the first end, and wherein the second end projects outwardly from a surface of the substrate. The method can further include forming a dielectric layer over the surface of the substrate and the second end of the conductive feature such that the dielectric layer has an original thickness. The method can also include removing a portion of the dielectric layer to an intermediate depth less than the original thickness such that at least a portion of the second end of the conductive feature is exposed.

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices. One example of a method of fabricating a semiconductor device comprises forming a conductive feature extending through a semiconductor substrate such that the conductive feature has a first end and a second end opposite the first end, and wherein the second end projects outwardly from a surface of the substrate. The method can further include forming a dielectric layer over the surface of the substrate and the second end of the conductive feature such that the dielectric layer has an original thickness. The method can also include removing a portion of the dielectric layer to an intermediate depth less than the original thickness such that at least a portion of the second end of the conductive feature is exposed.

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices. One example of a method of fabricating a semiconductor device comprises forming a conductive feature extending through a semiconductor substrate such that the conductive feature has a first end and a second end opposite the first end, and wherein the second end projects outwardly from a surface of the substrate. The method can further include forming a dielectric layer over the surface of the substrate and the second end of the conductive feature such that the dielectric layer has an original thickness. The method can also include removing a portion of the dielectric layer to an intermediate depth less than the original thickness such that at least a portion of the second end of the conductive feature is exposed.

Abstract: Pass-through interconnect structures for microelectronic dies and associated systems and methods are disclosed herein. In one embodiment, a microelectronic die assembly includes a support substrate, a first microelectronic die positioned at least partially over the support substrate, and a second microelectronic die positioned at least partially over the first die. The first die includes a semiconductor substrate, a conductive trace extending over a portion of the semiconductor substrate, a substrate pad between the trace and the portion of the semiconductor substrate, and a through-silicon via (TSV) extending through the trace, the substrate pad, and the portion of the semiconductor substrate. The second die is electrically coupled to the support substrate via a conductive path that includes the TSV.

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices. One example of a method of fabricating a semiconductor device comprises forming a conductive feature extending through a semiconductor substrate such that the conductive feature has a first end and a second end opposite the first end, and wherein the second end projects outwardly from a surface of the substrate. The method can further include forming a dielectric layer over the surface of the substrate and the second end of the conductive feature such that the dielectric layer has an original thickness. The method can also include removing a portion of the dielectric layer to an intermediate depth less than the original thickness such that at least a portion of the second end of the conductive feature is exposed.

Abstract: Stacked semiconductor devices, semiconductor assemblies, methods of manufacturing stacked semiconductor devices, and methods of manufacturing semiconductor assemblies. One embodiment of a semiconductor assembly comprises a thinned semiconductor wafer having an active side releasably attached to a temporary carrier, a back side, and a plurality of first dies at the active side. The individual first dies have an integrated circuit, first through die interconnects electrically connected to the integrated circuit, and interconnect contacts exposed at the back side of the wafer. The assembly further includes a plurality of separate second dies attached to corresponding first dies on a front side, wherein the individual second dies have integrated circuits, through die interconnects electrically connected to the integrated circuits and contact points at a back side, and wherein the individual second dies have a thickness of approximately less than 100 microns.

Abstract: Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a substrate, a metal substrate pad, and a first integrated circuit electrically coupled to the substrate pad. A pass-through 3D interconnect extends between front and back sides of the substrate, including through the substrate pad. The pass-through interconnect is electrically isolated from the substrate pad and electrically coupled to a second integrated circuit of a second microelectronic die attached to the back side of the substrate. In another embodiment, the first integrated circuit is a first memory device and the second integrated circuit is a second memory device, and the system uses the pass-through interconnect as part of an independent communication path to the second memory device.

Abstract: Stacked semiconductor devices, semiconductor assemblies, methods of manufacturing stacked semiconductor devices, and methods of manufacturing semiconductor assemblies. One embodiment of a semiconductor assembly comprises a thinned semiconductor wafer having an active side releaseably attached to a temporary carrier, a back side, and a plurality of first dies at the active side. The individual first dies have an integrated circuit, first through die interconnects electrically connected to the integrated circuit, and interconnect contacts exposed at the back side of the wafer. The assembly further includes a plurality of separate second dies attached to corresponding first dies on a front side, wherein the individual second dies have integrated circuits, through die interconnects electrically connected to the integrated circuits and contact points at a back side, and wherein the individual second dies have a thickness of approximately less than 100 microns.

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices. One example of a method of fabricating a semiconductor device comprises forming a conductive feature extending through a semiconductor substrate such that the conductive feature has a first end and a second end opposite the first end, and wherein the second end projects outwardly from a surface of the substrate. The method can further include forming a dielectric layer over the surface of the substrate and the second end of the conductive feature such that the dielectric layer has an original thickness. The method can also include removing a portion of the dielectric layer to an intermediate depth less than the original thickness such that at least a portion of the second end of the conductive feature is exposed.

Abstract: Stacked semiconductor devices, semiconductor assemblies, methods of manufacturing stacked semiconductor devices, and methods of manufacturing semiconductor assemblies. One embodiment of a semiconductor assembly comprises a thinned semiconductor wafer having an active side releaseably attached to a temporary carrier, a back side, and a plurality of first dies at the active side. The individual first dies have an integrated circuit, first through die interconnects electrically connected to the integrated circuit, and interconnect contacts exposed at the back side of the wafer. The assembly further includes a plurality of separate second dies attached to corresponding first dies on a front side, wherein the individual second dies have integrated circuits, through die interconnects electrically connected to the integrated circuits and contact points at a back side, and wherein the individual second dies have a thickness of approximately less than 100 microns.