Patents by Inventor David Steven Maitland

David Steven Maitland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Modular binary half-adder
    Patent number: 4054788
    Abstract: Half-adder logic modules employing separate summing and carry circuitry are used in the construction of a modular binary half-adder. Carry bits of less significant digits are calculated independent of and prior to the calculation of corresponding sum bits, thus allowing rapid propagation of such carry bits to more significant digits and subsequent parallel summation of the sum bits using the carry bits previously calculated.
    Type: Grant
    Filed: June 4, 1976
    Date of Patent: October 18, 1977
    Assignee: Hewlett-Packard Company
    Inventors: David Steven Maitland, Sandy Lee Chumbley, Havyn E. Bradley
  • Binary adder
    Patent number: 4052604
    Abstract: A binary adder employs separate summing and carry circuitry within each digit to optimize the speed of operation of the adder. Carry bits of less significant digits are calculated independently of corresponding sum bits, thus allowing propagation of such carry bits to more significant digits before completion of the summation of the less significant digits.
    Type: Grant
    Filed: January 19, 1976
    Date of Patent: October 4, 1977
    Assignee: Hewlett-Packard Company
    Inventors: David Steven Maitland, Billy E. Thayer
  • IGFET threshold voltage compensator
    Patent number: 4049980
    Abstract: A circuit is described which compensates for variation in the threshold voltage of Insulated Gate Field Effect Transistors (IGFETs) in an integrated circuit by modulating the substrate voltage in response to the variation of the threshold voltage from a desired nominal value.
    Type: Grant
    Filed: April 26, 1976
    Date of Patent: September 20, 1977
    Assignee: Hewlett-Packard Company
    Inventor: David Steven Maitland
  • Information transfer bus circuit with signal loss compensation
    Patent number: 4045684
    Abstract: An information transfer bus circuit useful in metal oxide semiconductor integrated circuits employs a network to compensate for signal losses arising from capacitance associated with gating devices in the circuit.
    Type: Grant
    Filed: January 19, 1976
    Date of Patent: August 30, 1977
    Assignee: Hewlett-Packard Company
    Inventors: William Donovan Eads, David Steven Maitland