Patents by Inventor David Strasser

David Strasser has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10509588
    Abstract: Systems, methods, and computer programs are disclosed for controlling memory frequency. One method comprises a first memory client generating a compressed data buffer and compression statistics related to the compressed data buffer. The compressed data buffer and the compression statistics are stored in a memory device. Based on the stored compression statistics, a frequency or voltage setting of the memory device is adjusted for enabling a second memory client to read the compressed data buffer.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: December 17, 2019
    Assignee: Qualcomm Incorporated
    Inventors: Serag Gadelrab, Sudeep Ravi Kottilingal, Meghal Varia, Pooja Sinha, Ujwal Patel, Ruo Long Liu, Jeffrey Chu, Sina Gholamian, Hyukjune Chung, David Strasser, Raghavendra Nagaraj, Eric Demers
  • Publication number: 20170083262
    Abstract: Systems, methods, and computer programs are disclosed for controlling memory frequency. One method comprises a first memory client generating a compressed data buffer and compression statistics related to the compressed data buffer. The compressed data buffer and the compression statistics are stored in a memory device. Based on the stored compression statistics, a frequency or voltage setting of the memory device is adjusted for enabling a second memory client to read the compressed data buffer.
    Type: Application
    Filed: January 13, 2016
    Publication date: March 23, 2017
    Inventors: SERAG GADELRAB, SUDEEP RAVI KOTTILINGAL, MEGHAL VARIA, POOJA SINHA, UJWAL PATEL, RUOLONG LIU, JEFFREY CHU, SINA GHOLAMIAN, HYUKJUNE CHUNG, DAVID STRASSER, RAGHAVENDRA NAGARAJ, ERIC DEMERS
  • Patent number: 7788505
    Abstract: A graphics processor receives a compressed encrypted video stream. The graphics processor decrypts the compressed encrypted video stream and stores a decrypted version (i.e., a decrypted compressed video stream) in a protected portion of an on-chip or off-chip video memory. The graphics processor then permits processors and other bus masters on the graphics processor to access the on-chip video memory, but conditionally limits access to other bus masters that are located off-chip, such as a central processing unit located off-chip and coupled to the graphics processor via a bus.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: August 31, 2010
    Assignee: ATI Technologies ULC
    Inventors: Allen J. C. Porter, Chun Wang, Kevork Kechichian, Gabriel Varga, David Strasser
  • Publication number: 20070146542
    Abstract: To receive new services including audio or video content for presentation by a cable-compatible digital television or other digital audio/video receiver, a module may be connected to the HOST-POD interface of the digital television. The module has a receiver for receiving audio or video content in a first compression format, a transcoder for converting said audio or video content from the first compression format into a second, different compression format, and a controller for transmitting the audio or visual content in the second compression format to the digital television over a HOST-POD interface. By using such a module, front-end components of the digital television may be bypassed while back-end components may be utilized to decompress and present the content. The module may be a PC card or smart card for example.
    Type: Application
    Filed: December 22, 2005
    Publication date: June 28, 2007
    Applicant: ATI TECHNOLOGIES INC.
    Inventor: David Strasser
  • Publication number: 20060209210
    Abstract: An apparatus and method provides automatic audio and video synchronization by calculating a video delay time period based on a signal processing routine to generate the video display signal and automatically setting an audio delay to approximate the video delay time period. In addition the method may include if desired, determining a master device from a plurality of master capable devices. The master device is a processing device including one or more processors capable of making configuration decisions and designating a data flow for rendering a video signal. The master-capable devices are any suitable processing devices which are capable of acting as a master device. The present invention may further include using the master device to determine a signal processing routine to generate a video display signal.
    Type: Application
    Filed: March 18, 2005
    Publication date: September 21, 2006
    Applicant: ATI TECHNOLOGIES INC.
    Inventors: Philip Swan, David Strasser
  • Publication number: 20060176909
    Abstract: When a stream of packets (e.g. MPEG-2 transport stream) includes certain packets representing unscrambled digital television program content and certain other packets representing the content of a scrambled digital television program that is currently tuned by a receiver, interception of the unscrambled digital television program at an output of the receiver may be prevented by determining whether packets representing program content have an ascertained characteristic (e.g. have a packet ID matching one of a set of packet IDs) that uniquely identifies the packets as representing content of the scrambled program. For packets not having the characteristic, delivery to the output of the digital television receiver in an unscrambled state may be prevented, e.g., by discarding the packet or by overwriting its payload.
    Type: Application
    Filed: February 9, 2005
    Publication date: August 10, 2006
    Applicant: ATI Technologies Inc.
    Inventor: David Strasser
  • Publication number: 20060140585
    Abstract: To detect at least one of a copy protection indicator and a redistribution control indicator in an analog video signal, the video format of the analog video signal is determined, e.g., by detecting the horizontal frequency and vertical frequency of the signal. Based at least on the determined video format, a region of the analog video signal that may contain the indicator is identified. The region may for example be one or more video lines in a vertical blanking interval. The region is examined until the indicator is detected. The indicator is confirmed, e.g., by re-detecting one or more occurrences of the same indicator value(s) later in the video signal. Once confirmed, the indicated copy protection and/or redistribution control may be effected by limiting either or both of copying and redistribution of the analog video signal. The indicator may for example be Copy Generation Management System Analog plus Redistribution Control (CGMS-A+RC) information.
    Type: Application
    Filed: December 23, 2004
    Publication date: June 29, 2006
    Inventor: David Strasser
  • Publication number: 20060123248
    Abstract: A graphics processor receives a compressed encrypted video stream. The graphics processor decrypts the compressed encrypted video stream and stores a decrypted version (i.e., a decrypted compressed video stream) in a protected portion of an on-chip or off-chip video memory. The graphics processor then permits processors and other bus masters on the graphics processor to access the on-chip video memory, but conditionally limits access to other bus masters that are located off-chip, such as a central processing unit located off-chip and coupled to the graphics processor via a bus.
    Type: Application
    Filed: December 14, 2005
    Publication date: June 8, 2006
    Inventors: Allen Porter, Chun Wang, Kevork Kechichian, Gabriel Varga, David Strasser
  • Patent number: 7055038
    Abstract: A graphics processor receives a compressed encrypted video stream. The graphics processor decrypts the compressed encrypted video stream and stores a decrypted version (i.e., a decrypted compressed video stream) in a protected portion of an on-chip or off-chip video memory. The graphics processor then permits processors and other bus masters on the graphics processor to access the on-chip video memory, but conditionally limits access to other bus masters that are located off-chip, such as a central processing unit located off-chip and coupled to the graphics processor via a bus.
    Type: Grant
    Filed: May 7, 2001
    Date of Patent: May 30, 2006
    Assignee: ATI International SRL
    Inventors: Allen J. C. Porter, Chun Wang, Kevork Kechichian, Gabriel Varga, David Strasser
  • Publication number: 20050265547
    Abstract: A copy protection (CP) key used by a sending source, such as a POD, to encrypt content such as audio and/or video information is derived by a first key generator associated with a first processor and is locally encrypted by the first processor using a locally generated bus encryption key to produce a bus encrypted CP key that is sent over a local unsecure bus to a second processor, such as a graphics processor. The second processor decrypts the bus encrypted copy key using a decryption engine to obtain the CP key. The second processor receives the encrypted content and in one embodiment, also uses the same decryption engine to decrypt the encrypted content. The first and second processors locally exchange public keys to each locally derive a bus encryption key used to encrypt the CP key before it is sent over the unsecure bus and decrypt the encrypted CP key after it is sent over the bus.
    Type: Application
    Filed: July 6, 2005
    Publication date: December 1, 2005
    Inventors: David Strasser, Edwin Pang, Gabriel Varga
  • Publication number: 20020163522
    Abstract: A graphics processor receives a compressed encrypted video stream. The graphics processor decrypts the compressed encrypted video stream and stores a decrypted version (i.e., a decrypted compressed video stream) in a protected portion of an on-chip or off-chip video memory. The graphics processor then permits processors and other bus masters on the graphics processor to access the on-chip video memory, but conditionally limits access to other bus masters that are located off-chip, such as a central processing unit located off-chip and coupled to the graphics processor via a bus.
    Type: Application
    Filed: May 7, 2001
    Publication date: November 7, 2002
    Inventors: Allen J.C. Porter, Chun Wang, Kevork Kechichian, Gabriel Varga, David Strasser
  • Patent number: 6335761
    Abstract: A method and apparatus for converting the color base of an image input layer include processing that begins by interpreting a conversion flag. The processing then continues by converting the color base of the image input layer from a first color base to a second color base when the conversion flag indicates a color base conversion. Note that a color base corresponds to standardized colorometries of video signals, color space of video signals, and/or any other displaying characteristics of video signals that are standardized or may be subsequently standardized. Further note that an image input layer corresponds to a display or portion thereof (e.g., a window or a picture in picture), wherein the display is capable of presenting images from multiple video and/or graphics data sources (e.g., a television signal and a computer application).
    Type: Grant
    Filed: December 15, 1998
    Date of Patent: January 1, 2002
    Assignee: ATI International S.R.L.
    Inventors: David I. J. Glen, Michael Frank, David Strasser