Patents by Inventor David Strube
David Strube has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Methods and apparatus for efficient complex long multiplication and covariance matrix implementation
Patent number: 9075651Abstract: Efficient computation of complex long multiplication results and an efficient calculation of a covariance matrix are described. A parallel array VLIW digital signal processor is employed along with specialized complex long multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs may be used allowing the complex multiplication pipeline hardware to be efficiently used.Type: GrantFiled: September 13, 2012Date of Patent: July 7, 2015Assignee: Altera CorporationInventors: Gerald George Pechanek, Ricardo Rodriguez, Matthew Plonski, David Strube, Kevin Coopman -
Patent number: 9009365Abstract: Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.Type: GrantFiled: February 20, 2013Date of Patent: April 14, 2015Assignee: Altera CorporationInventors: Gerald George Pechanek, David Strube, Edwin Franklin Barry, Charles W. Kurak, Jr., Carl Donald Busboom, Dale Edward Schneider, Nikos P. Pitsianis, Grayson Morris, Edward A. Wolff, Patrick R. Marchand, Ricardo Rodriguez, Marco Jacobs
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Publication number: 20140059324Abstract: Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.Type: ApplicationFiled: February 20, 2013Publication date: February 27, 2014Inventors: Gerald George Pechanek, David Strube, Edwin Franklin Barry, Charles W. Kurak, JR., Carl Donald Busboom, Dale Edward Schneider, Nikos P. Pitsianis, Grayson Morris, Edward A. Wolff, Patrick R. Marchand, Ricardo Rodriguez, Marco Jacobs
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Patent number: 8397000Abstract: Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.Type: GrantFiled: September 12, 2012Date of Patent: March 12, 2013Assignee: Altera CorporationInventors: Gerald George Pechanek, David Strube, Edwin Franklin Barry, Charles W. Kurak, Jr., Carl Donald Busboom, Dale Edward Schneider, Nikos P. Pitsianis, Grayson Morris, Edward A. Wolff, Patrick R. Marchand, Ricardo E. Rodriguez, Marco C. Jacobs
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Methods and Apparatus for Efficient Complex Long Multiplication and Covariance Matrix Implementation
Publication number: 20130007421Abstract: Efficient computation of complex long multiplication results and an efficient calculation of a covariance matrix are described. A parallel array VLIW digital signal processor is employed along with specialized complex long multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs may be used allowing the complex multiplication pipeline hardware to be efficiently used.Type: ApplicationFiled: September 13, 2012Publication date: January 3, 2013Applicant: ALTERA CORPORATIONInventors: Gerald G. Pechanek, Ricardo Rodriguez, Matthew Plonski, David Strube, Kevin Coopman -
Methods and apparatus for efficient complex long multiplication and covariance matrix implementation
Patent number: 8335812Abstract: Efficient computation of complex long multiplication results and an efficient calculation of a covariance matrix are described. A parallel array VLIW digital signal processor is employed along with specialized complex long multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs may be used allowing the complex multiplication pipeline hardware to be efficiently used.Type: GrantFiled: January 19, 2010Date of Patent: December 18, 2012Assignee: Altera CorporationInventors: Gerald George Pechanek, Ricardo Rodriguez, Matthew Plonski, David Strube, Kevin Coopman -
Patent number: 8296479Abstract: Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.Type: GrantFiled: January 5, 2012Date of Patent: October 23, 2012Assignee: Altera CorporationInventors: Gerald George Pechanek, David Strube, Edwin Franklin Barry, Charles W. Kurak, Jr., Carl Donald Busboom, Dale Edward Schneider, Nikos P. Pitsianis, Grayson Morris, Edward A. Wolff, Patrick R. Marchand, Ricardo E. Rodriguez, Marco C. Jacobs
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Methods and apparatus for efficient complex long multiplication and covariance matrix implementation
Publication number: 20100121899Abstract: Efficient computation of complex long multiplication results and an efficient calculation of a covariance matrix are described. A parallel array VLIW digital signal processor is employed along with specialized complex long multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs may be used allowing the complex multiplication pipeline hardware to be efficiently used.Type: ApplicationFiled: January 19, 2010Publication date: May 13, 2010Applicant: Altera CorporationInventors: Gerald G. Pechanek, Ricardo Rodriguez, Matthew Plonski, David Strube, Kevin Coopman -
Methods and apparatus for efficient complex long multiplication and covariance matrix implementation
Patent number: 7680873Abstract: Efficient computation of complex long multiplication results and an efficient calculation of a covariance matrix are described. A parallel array VLIW digital signal processor is employed along with specialized complex long multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs may be used allowing the complex multiplication pipeline hardware to be efficiently used.Type: GrantFiled: May 22, 2006Date of Patent: March 16, 2010Assignee: Altera CorporationInventors: Gerald George Pechanek, Ricardo Rodriguez, Matthew Plonski, David Strube, Kevin Coopman -
Patent number: 7506137Abstract: Techniques for adding more complex instructions and their attendant multi-cycle execution units with a single instruction multiple data stream (SIMD) very long instruction word (VLIW) processing framework are described. In one aspect, an initiation mechanism also acts as a resynchronization mechanism to read the results of multi-cycle execution. This multi-purpose mechanism operates with a short instruction word (SIW) issue of the multi-cycle instruction, in a sequence processor (SP) alone, with a VLIW, and across all processing elements (PEs) individually or as an array of PEs. A number of advantageous floating point instructions are also described.Type: GrantFiled: July 16, 2007Date of Patent: March 17, 2009Assignee: Altera CorporationInventors: Gerald George Pechanek, David Strube, Edward A. Wolff, Edwin Franklin Barry, Grayson Morris, Carl Donald Busboom, Dale Edward Schneider
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Patent number: 7266620Abstract: A system core having an internal memory which transfers data from an external device to the internal memory is described. To this end, the system core includes a processor, a direct memory access (DMA) controller, an instruction memory and a plurality of memories. The instruction memory contains processor instructions and DMA instructions. The DMA controller fetches DMA instructions from the instruction memory. The DMA controller executes the fetched DMA instructions and thus populates the plurality of memories with data from the external device. The processor then operates on the data found in the populated memories.Type: GrantFiled: March 10, 2004Date of Patent: September 4, 2007Assignee: Altera CorporationInventors: Gerald George Pechanek, David Strube, Edwin Franklin Barry, Charles W. Kurak, Jr., Carl Donald Busboom, Dale Edward Schneider, Nikos P. Pitsianis, Grayson Morris, Edward A. Wolff, Patrick R. Marchand, Ricardo E. Rodriguez, Marco C. Jacobs
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Patent number: 7257696Abstract: Techniques for adding more complex instructions and their attendant multi-cycle execution units with a single instruction multiple data stream (SIMD) very long instruction word (VLIW) processing framework are described. In one aspect, an initiation mechanism also acts as a resynchronization mechanism to read the results of multi-cycle execution. This multi-purpose mechanism operates with a short instruction word (SIW) issue of the multi-cycle instruction, in a sequence processor (SP) alone, with a VLIW, and across all processing elements (PEs) individually or as an array of PEs. A number of advantageous floating point instructions are also described.Type: GrantFiled: August 15, 2003Date of Patent: August 14, 2007Assignee: Altera CorporationInventors: Gerald George Pechanek, David Strube, Edward A. Wolff, Edwin Franklin Barry, Grayson Morris, Carl Donald Busboom, Dale Edward Schneider
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Patent number: 7237088Abstract: The ManArray core indirect VLIW processor consists of an array controller sequence processor (SP) merged with a processing element (PE0) closely coupling the SP with the PE array and providing the capability to share execution units between the SP and PE0. Consequently, in the merged SP/PE0 a single set of execution units are coupled with two independent register files. To make efficient use of the SP and PE resources, the ManArray architecture specifies a bit in the instruction format, the SP/PE-bit, to differentiate SP instructions from PE instructions. Multiple register contexts are obtained in the ManArray processor by controlling how the array SP/PE-bit in the ManArray instruction format is used in conjunction with a context switch bit (CSB) for the context selection of the PE register file or the SP register file.Type: GrantFiled: January 21, 2004Date of Patent: June 26, 2007Assignee: Altera CorporationInventors: Edwin Franklin Barry, Gerald George Pechanek, David Strube
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Methods and apparatus for efficient complex long multiplication and covariance matrix implementation
Publication number: 20060224656Abstract: Efficient computation of complex long multiplication results and an efficient calculation of a covariance matrix are described. A parallel array VLIW digital signal processor is employed along with specialized complex long multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs may be used allowing the complex multiplication pipeline hardware to be efficiently used.Type: ApplicationFiled: May 22, 2006Publication date: October 5, 2006Applicant: PTS CorporationInventors: Gerald Pechanek, Ricardo Rodriguez, Matthew Plonski, David Strube, Kevin Coopman -
Patent number: 7103621Abstract: Efficient techniques for computation of texture coordinates using scaled conversion operations for a 3D graphics pipeline utilizing a scaled floating point to integer instruction and a scaled integer to floating point instruction to significantly reduce memory requirements. A parallel array VLIW digital signal processor is employed along with specialized scaled conversion instructions and communication operations between the processing elements, which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the graphics pipeline hardware to be efficiently used.Type: GrantFiled: March 31, 2003Date of Patent: September 5, 2006Assignee: PTS CorporationInventors: Ricardo Rodriguez, Marco Jacobs, David Strube
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Methods and apparatus for efficient complex long multiplication and covariance matrix implementation
Patent number: 7072929Abstract: A digital signal processor for computing various types of complex multiplication is described. The digital signal processor operates in conjunction with registers, a multiplier, an adder, and a multiplexer The Registers store first and second complex operands. The multiplier simultaneously performs multiplications to produce each combination of products between the real and imaginary terms of the first and second complex operands. The multiplexer selects which produced products are added to or subtracted from each other based on the type of complex multiplication being performed. The adder simultaneously performs additions and subtractions, if necessary, to produce both real and imaginary results depending on whether the type of complex multiplication being performed is a conjugated operation. The registers store the results of the complex multiplication.Type: GrantFiled: November 1, 2001Date of Patent: July 4, 2006Assignee: PTS CorporationInventors: Gerald G. Pechanek, Ricardo Rodriguez, Matthew Plonski, David Strube, Kevin Coopman -
Publication number: 20040113914Abstract: Efficient techniques for computation of texture coordinates using scaled conversion operations for a 3D graphics pipeline utilizing a scaled floating point to integer instruction and a scaled integer to floating point instruction to significantly reduce memory requirements. A parallel array VLIW digital signal processor is employed along with specialized scaled conversion instructions and communication operations between the processing elements, which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the graphics pipeline hardware to be efficiently used.Type: ApplicationFiled: March 31, 2003Publication date: June 17, 2004Applicant: PTS CorporationInventors: Ricardo Rodriguez, Marco Jacobs, David Strube
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Methods and apparatus for efficient complex long multiplication and covariance matrix implementation
Publication number: 20020169813Abstract: Efficient computation of complex long multiplication results and an efficient calculation of a covariance matrix are described. A parallel array VLIW digital signal processor is employed along with specialized complex long multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs may be used allowing the complex multiplication pipeline hardware to be efficiently used.Type: ApplicationFiled: November 1, 2001Publication date: November 14, 2002Applicant: BOPS, Inc.Inventors: Gerald G. Pechanek, Ricardo Rodriguez, Matthew Plonski, David Strube, Kevin Coopman -
Patent number: RE41703Abstract: A SIMD machine employing a plurality of parallel processor (PEs) in which communications hazards are eliminated in an efficient manner. An indirect Very Long Instruction Word instruction memory (VIM) is employed along with execute and delimiter instructions. A masking mechanism may be employed to control which PEs have their VIMs loaded. Further, a receive model of operation is preferably employed. In one aspect, each PE operates to control a switch that selects from which PE it receives. The present invention addresses a better machine organization for execution of parallel algorithms that reduces hardware cost and complexity while maintaining the best characteristics of both SIMD and MIMD machines and minimizing communication latency. This invention brings a level of MIMD computational autonomy to SIMD indirect Very Long Instruction Word (iVLIW) processing elements while maintaining the single thread of control used in the SIMD machine organization.Type: GrantFiled: June 21, 2004Date of Patent: September 14, 2010Assignee: Altera Corp.Inventors: Gerald George Pechanek, Thomas L. Drabenstott, Juan Guillermo Revilla, David Strube, Grayson Morris