Abstract: A method of determining the distance from an edge feature to a wafer edge. The wafer is put onto an image acquisition tool, and images are captured and classified. Based on the coordinates of the images and their classifications, the distance between an edge feature and the wafer edge is determined. Reference marks can be etched into the wafer to facilitate the measurement. The measurement technique is objective, and can be used to minimize the edge exclusion ring as well as defects that originate from the edge of the wafer.

Abstract: A method for multistage routing of packets using call templates is disclosed. An ingress call is filtered based on a plurality of ingress-call parameter values. A parameter value for the ingress call is modified based on a plurality of ingress-call-peer parameter values. A filtered ingress-call parameter value and at least one filtered ingress-call-peer parameter value from a plurality of ingress-call-peer parameter values are converted to an egress-call parameter value and an egress-call-peer parameter value, respectively. An egress call is filtered based on a plurality of egress-call parameter values. A parameter value for the egress call is modified based on a plurality of egress-call-peer parameter values.

Abstract: A layered test pattern for measuring registration and critical dimension (CD) for multi-layer semiconductor integrated circuits is disclosed. A first layer includes a first pattern having vertical and horizontal portions. A second layer is formed over the first layer and includes a second pattern having vertical and horizontal portions having nominal vertical and horizontal phase shifts with respect to the vertical and horizontal portions, respectively, of the first pattern. The vertical and horizontal portions include periodically repeating vertical lines and horizontal lines, respectively. The nominal phase shifts may be half of the period of the vertical and horizontal lines. A scatterometry tool measures the width of the lines and the phase shift of the first pattern relative to the second pattern. The width of the lines corresponds to CD, whereas the difference between the measured phase shift and the nominal phase shift indicates variation in registration.

Abstract: A layered test pattern for measuring registration and critical dimension (CD) for multi-layer semiconductor integrated circuits is disclosed. A first layer includes a first pattern having vertical and horizontal portions. A second layer is formed over the first layer and includes a second pattern having vertical and horizontal portions having nominal vertical and horizontal phase shifts with respect to the vertical and horizontal portions, respectively, of the first pattern. The vertical and horizontal portions include periodically repeating vertical lines and horizontal lines, respectively. The nominal phase shifts may be half of the period of the vertical and horizontal lines. A scatterometry tool measures the width of the lines and the phase shift of the first pattern relative to the second pattern. The width of the lines corresponds to CD, whereas the difference between the measured phase shift and the nominal phase shift indicates variation in registration.

Abstract: A method and file structure for exposing images from a plurality of reticles onto a wafer. Multiple images are effectively merged into the same file, which means the wafer need not be unloaded from a stage while exposing multiple reticles. For example, every odd numbered column can contain images from one reticle, and every even numbered column can contain images from a second reticle, where image shifts are used to align the patterns exactly. A continuous pattern is utilized to mimic normal wafer processing.

Abstract: A method of fabricating a plurality of integrated circuits on a substrate according to a first integrated circuit design. Each of the integrated circuits is formed with a plurality of layer patterns. At least one first layer pattern of the layer patterns is common with a second integrated circuit design, and at least one second layer pattern of the layer patterns is unique to the first integrated circuit design. The first layer pattern is imaged on the substrate using an exposure tool and a first mask having a first number of the first layer patterns formed in a block thereon. No other layer patterns of the first layer patterns and the second layer patterns are formed on the first mask. The first number is less than the plurality of integrated circuits formed on the substrate. The first layer patterns are imaged on the substrate by exposing and repeating the block of first number of first layer patterns across the substrate with the exposure tool.

Abstract: A method of printing an image on a wafer. The method includes the steps of printing a main image, wherein the main image includes fields which are fully on the wafer, and printing an alternate image, wherein the alternate image includes fields which are only partially on the wafer. The alternate image could be placed on a separate mask which is loaded onto the exposure tool after the mask with the main image has completed printing. Alternatively, it could be an extra image specially inserted on the mask with the main image for that layer.

Abstract: A method of determining the distance from an edge feature to a wafer edge. The wafer is put onto an image acquisition tool, and images are captured and classified. Based on the coordinates of the images and their classifications, the distance between an edge feature and the wafer edge is determined. Reference marks can be etched into the wafer to facilitate the measurement. The measurement technique is objective, and can be used to minimize the edge exclusion ring as well as defects that originate from the edge of the wafer.

Abstract: A graphical profile map for integrated circuits on a substrate. The graphical profile map includes a depiction of die placement boundaries and shot placement boundaries for the integrated circuits on the substrate. Also included are integrated circuit property information contours, where the contours are not limited to either of the die placement boundaries or the shot placement boundaries. In this manner, three key pieces of information for the integrated circuits are presented, including integrated circuit property information, die placement, and shot placement. Because these three pieces of information are presented in a graphical form, it is much easier to interpret the information. For example, it is much easier to determine which shot and die placements have properties that are at risk, and which shot and die placements have adequate property profiles.