Abstract: A method of operating a processing unit includes, in response to detecting that the processing unit is operating in a voltage limited state, calculating a set of headroom values by calculating a headroom value for each operational constraint in a set of operational constraints of the processing unit, based on the calculated set of headroom values, selecting from a set of performance features a subset of one or more performance features for enabling in the processing unit, and enabling the selected subset of performance features in the processing unit.

Abstract: A method of operating a processing unit includes, in response to detecting that the processing unit is operating in a voltage limited state, calculating a set of headroom values by calculating a headroom value for each operational constraint in a set of operational constraints of the processing unit, based on the calculated set of headroom values, selecting from a set of performance features a subset of one or more performance features for enabling in the processing unit, and enabling the selected subset of performance features in the processing unit.

Abstract: A system and method for efficient improvement of branch prediction in a microprocessor with negligible impact on die-area, power consumption, and clock cycle period. It is determined if a program counter (PC) register contains a polymorphic indirect unconditional branch (PIUB) instruction. One determination may be searching a table with a portion or all of a PC of past PIUB instructions. If a hit occurs in this table, the global shift register (GSR) is updated by shifting a portion of the branch target address into the GSR, rather than updating the GSR with a taken/not-taken prediction bit. The stored value in the GSR is input into a hashing function along with the PC in order to index prediction tables such as a pattern history table (PHT), a branch target buffer (BTB), an indirect target array, or other. The updated value due to the PIUB instruction improves the accuracy of the prediction tables.

Abstract: Techniques are disclosed relating to improving the performance of branch prediction in processors. In one embodiment, a processor is disclosed that includes a branch prediction unit configured to predict a sequence of instructions to be issued by the processor for execution. The processor also includes a pattern detection unit configured to detect a pattern in the predicted sequence of instructions, where the pattern includes a plurality of predicted instructions. In response to the pattern detection unit detecting the pattern, the processor is configured to switch from issuing instructions predicted by the branch prediction unit to issuing the plurality of instructions. In some embodiments, the processor includes a replay unit that is configured to replay fetch addresses to an instruction fetch unit to cause the plurality of predicted instructions to be issued.

Abstract: Techniques are disclosed relating to improving the performance of branch prediction in processors. In one embodiment, a processor is disclosed that includes a branch prediction unit configured to predict a sequence of instructions to be issued by the processor for execution. The processor also includes a pattern detection unit configured to detect a pattern in the predicted sequence of instructions, where the pattern includes a plurality of predicted instructions. In response to the pattern detection unit detecting the pattern, the processor is configured to switch from issuing instructions predicted by the branch prediction unit to issuing the plurality of instructions. In some embodiments, the processor includes a replay unit that is configured to replay fetch addresses to an instruction fetch unit to cause the plurality of predicted instructions to be issued.

Abstract: The present invention provides an electrically driven oxygen separation assembly and method of applying an electrical potential thereto in which one or more tubular membrane elements are provided having an anode layer, a cathode layer, an electrolyte layer and two current collector layers adjacent to and in contact with the anode layer and the cathode layer and situated on the inside and outside of the at least one tubular membrane element. The potential is applied to one of the two current collector layers at two central spaced locations of the at least one tubular membrane element and to the other of the two current collector layers at least at opposite end locations thereof. As a result the electric current flow through the tubular membrane element is divided into two parts flowing between the two central spaced locations and the opposite end locations.

Abstract: A system and method for efficient improvement of branch prediction in a microprocessor with negligible impact on die-area, power consumption, and clock cycle period. It is determined if a program counter (PC) register contains a polymorphic indirect unconditional branch (PIUB) instruction. One determination may be searching a table with a portion or all of a PC of past PIUB instructions. If a hit occurs in this table, the global shift register (GSR) is updated by shifting a portion of the branch target address into the GSR, rather than updating the GSR with a taken/not-taken prediction bit. The stored value in the GSR is input into a hashing function along with the PC in order to index prediction tables such as a pattern history table (PHT), a branch target buffer (BTB), an indirect target array, or other. The updated value due to the PIUB instruction improves the accuracy of the prediction tables.

Abstract: A system and method is provided for performing sound synthesis with delay-based special effects which may be algorithmically implemented using one or more time-delay elements The system implements the time-delay elements by using system memory to store time-delay data. The system and method described herein utilizes the benefits of a high bandwidth I/O bus while mitigating the disadvantages introduced by having to arbitrate for a shared system bus. By using system memory for storing time-delay data, a more cost effective PC audio system can be produced.

Abstract: A hazard-free digital pulse divider circuit is provided which enables an output having a period one and one-half times that of the input pulse signal. Means for selectively extending output pulse in full or half period increments are also provided.