Abstract: Reliable memory modules are assembled from partially-tested memory chips that are neither individually burned-in nor fully tested. Instead, individual memory chips are partially tested to screen out gross failures and then assembled into memory modules that are inserted into memory-module burn-in boards and placed into a burn-in oven. The memory modules are stressed during burn-in by high temperatures and applied voltages. After burn-in, the memory modules are removed from the memory-module burn-in boards and extensively tested. Functional tests include many test patterns to test all memory locations in the partially-tested memory chips on the memory modules. Tests are performed at corner conditions such as high temperature and voltage. Infant mortality and single-bit faults are detected by the functional tests after module burn-in. The number of insertions into burn-in boards is reduced by the number of memory chips per module minus one, so handling and test costs are reduced.

Abstract: A repairing fully-buffered memory module can have memory chips with some defects such as single-bit errors. A repair controller is added to the Advanced Memory Buffer (AMB) on the memory module. The AMB fully buffers memory requests that are sent as serial packets over southbound lanes from a host. Memory-access addresses are extracted from the serial packets by the AMB. The repair controller compares the memory-access addresses to repair addresses and diverts access from defective memory chips to a spare memory for the repair addresses. The repair addresses can be located during testing of the memory module and programmed into a repair address buffer on the AMB. The repair addresses could be first programmed into a serial-presence-detect electrically-erasable programmable read-only memory (SPD-EEPROM) on the memory module, and then copied to the repair address buffer on the AMB during power-up.

Abstract: Memory chips are tested by insertion into a chip test socket on a test adapter board that is mounted to the reverse or solder-side of a personal computer motherboard. A memory module socket is removed from the motherboard, and adapter pins are inserted into holes for the removed memory module socket, but from the reverse (solder) side of the motherboard. The adapter pins connect to the test adapter board either directly, through a connector plug, or through an intervening adapter board. The test adapter board has soldered onto it additional memory chips and buffer chips on a memory module, such as an Advanced Memory Buffer (AMB) for a fully-buffered memory module. The built-in-self-test (BIST) feature of the AMB may be used to test the memory chip under test in the chip test socket, or the processor on the motherboard may write and read the memory chip.

Abstract: A repairing fully-buffered memory module can have memory chips with some defects such as single-bit errors. A repair controller is added to the Advanced Memory Buffer (AMB) on the memory module. The AMB fully buffers memory requests that are sent as serial packets over southbound lanes from a host. Memory-access addresses are extracted from the serial packets by the AMB. The repair controller compares the memory-access addresses to repair addresses and diverts access from defective memory chips to a spare memory for the repair addresses. The repair addresses can be located during testing of the memory module and programmed into a repair address buffer on the AMB. The repair addresses could be first programmed into a serial-presence-detect electrically-erasable programmable read-only memory (SPD-EEPROM) on the memory module, and then copied to the repair address buffer on the AMB during power-up.

Abstract: A Flash memory controller is disclosed. The Flash memory controller comprises a host interface, a Flash memory interface, controller logic coupled between the host interface the controller logic handling a plurality of voltages. The controller also includes a mechanism for allowing a multiple voltage host to interface with a high voltage or a multiple voltage Flash memory. A multiple voltage Flash memory controller in accordance with the present invention provides the following advantages over conventional Flash memory controllers: (1) a voltage host is allowed to interface with multiple Flash memory components that operate at different voltages in any combination; (2) power consumption efficiency is improved by integrating the programmable voltage regulator, and voltage comparator mechanism with the Flash memory controller; (3) External jumper selection is eliminated for power source configuration; and (4) Flash memory controller power source interface pin-outs are simplified.

Abstract: A repairing fully-buffered memory module can have memory chips with some defects such as single-bit errors. A repair controller is added to the Advanced Memory Buffer (AMB) on the memory module. The AMB fully buffers memory requests that are sent as serial packets over southbound lanes from a host. Memory-access addresses are extracted from the serial packets by the AMB. The repair controller compares the memory-access addresses to repair addresses and diverts access from defective memory chips to a spare memory for the repair addresses. The repair addresses can be located during testing of the memory module and programmed into a repair address buffer on the AMB. The repair addresses could be first programmed into a serial-presence-detect electrically-erasable programmable read-only memory (SPD-EEPROM) on the memory module, and then copied to the repair address buffer on the AMB during power-up.

Abstract: An error-correcting fully-buffered memory module can detect and correct some errors in data read from memory chips. An error correction code ECC controller is added to the Advanced Memory Buffer (AMB) on the memory module that fully buffers memory requests sent as serial packets. The error correction controller generates ECC bits for write data, and both the ECC bits and the write data are written to the memory chips by a DRAM controller in the AMB. During reads, an ECC checker generates a syndrome and can activate an error corrector to correct data or signal a non-correctable error. The corrected data is formed into serial packets sent back to the motherboard by the AMB. Configuration data for the ECC controller could be first programmed into a serial-presence-detect electrically-erasable programmable read-only memory (SPD-EEPROM) on the memory module, and then copied to error-correction configuration registers on the AMB during power-up.

Abstract: Fluidic methods and devices for conducting parallel chemical reactions are disclosed. The methods are based on the use of in situ photogenerated reagents such as photogenerated acids, photogenerated bases, or any other suitable chemical compounds that produce active reagents upon light radiation. The present invention describes devices and methods for performing a large number of parallel chemical reactions without the use of a large number of valves, pumps, and other complicated fluidic components. The present invention provides microfluidic devices that contain a plurality of microscopic vessels for carrying out discrete chemical reactions.

Abstract: Reliable memory modules are assembled from partially-tested memory chips that are neither individually burned-in nor fully tested. Instead, individual memory chips are partially tested to screen out gross failures and then assembled into memory modules that are inserted into memory-module burn-in boards and placed into a burn-in oven. The memory modules are stressed during burn-in by high temperatures and applied voltages. After burn-in, the memory modules are removed from the memory-module burn-in boards and extensively tested. Functional tests include many test patterns to test all memory locations in the partially-tested memory chips on the memory modules. Tests are performed at corner conditions such as high temperature and voltage. Infant mortality and single-bit faults are detected by the functional tests after module burn-in. The number of insertions into burn-in boards is reduced by the number of memory chips per module minus one, so handling and test costs are reduced.

Abstract: Method and system for expanding the memory capacity of devices that use flash memory cards. In one aspect, a memory card expander assembly includes an adaptor shaped to be connected to a memory card slot of a host device, and a receptacle assembly in communication with the adaptor and operative to be attached to the host device. The receptacle assembly includes an expanded memory card slot operative to connect to a memory card such that the host device can communicate with the connected memory card when the adaptor is connected to the memory card slot.

Abstract: A pedal propulsion mechanism has a first crank arm mechanically connecting to a first gear set and a drive wheel. A second crank arm mechanically connects to a second gear set and the drive wheel. On a first crank arm power stroke the first crank arm drives the drive wheel and first gear set driving a second gear set driving the second crank arm. The first and second gear set have a gear ratio so that on a first crank arm power stroke the first crank arm drives the drive wheel and also drives the first gear set that drives a second gear set that drives the second crank arm at a rotational speed different than that of the first crank arm.

Abstract: A Flash memory card system is disclosed. The Flash memory card system comprises a Flash memory wireless host adapter and a Flash memory bus wireless device. The Flash memory wireless host adapter comprises a Flash memory card connector and a Flash memory controller coupled to the Flash memory card connector. The Flash-52 memory card signals are converted to standard Flash memory internal bus signals by the Flash memory controller. The host adapter further comprises a Flash memory wireless module coupled to the Flash memory controller for receiving and transmitting the standard Flash memory bus signals wirelessly. The Flash-51 memory bus wireless device comprises a Flash memory bus wireless device adapter coupled to a Flash memory. The device adapter is paired to the wireless module for receiving and transmitting the standard Flash memory bus signals wirelessly. A host device storage capacity utilizing the Flash memory card system is expanded.

Abstract: A downgraded memory module has downgraded DRAM chips soldered to its substrate. The downgraded DRAM chips have a defective memory cell in a logical quadrant of the memory. A physical MSB is a row address present on a non-downgraded DRAM of size S but not used on a downgraded DRAM size S/2. The physical MSB and a second address pin are non-multiplexed address pins that do not carry column addresses. The physical MSB and the second address pin logically divided the DRAM into quadrants. Two good quadrants without defects are selected, and jumpers on the memory module drive the physical MSB and the second address pin with signals that select only these two quadrants and disable access to quadrants containing defects. DRAM chips can be marked or sorted into bins for combinations of good quadrants. Downgraded memory modules have all DRAM chips from the same bin that share jumper settings.

Abstract: The present invention concerns an electronic forensic tool for conducting electronic discovery and computer forensic analysis. The present invention allows a non-technical person such as a non-forensic expert to conduct electronic discovery and thereby obviate the need for an expert in many situations. The present invention allows for electronic discovery in a forensically sound manner. The present invention also concerns a business method for electronic discovery involving a software program and a command server for generating expanded functionality. The client software may be distributed at minimal or no cost, preferably as a CD. Using the client software, a user boots a target machine to determine whether a target machine contains data of interest. The client software will, however, only display limited data such as file information, date, last modified, and file size. To access and examine the actual underlying data, the user must obtain additional functionality, e.g.

Abstract: Memory modules with an extra dynamic-random-access memory (DRAM) chip for storing error-correction code (ECC) are tested on a personal computer (PC) motherboard tester using a cross-over extender card inserted into a memory module socket on the motherboard. ECC code generated on the motherboard is normally stored in the extra ECC DRAM chip, preventing test patterns such as checkerboards and walking-ones to be written directly to the ECC DRAM chip. During testing, the cross-over extender card routes signals from the motherboard for one of the data DRAM chips to the ECC DRAM chip, while the ECC code is routed to one of the data DRAM chips. The checkerboard or other test pattern is thus written and read from the ECC DRAM chip that normally stores the ECC code. The cross-over extender card can be hardwired, or can have a switch to allow normal operation or testing of the ECC DRAM chip.

Abstract: The present invention concerns an electronic forensic tool for conducting electronic discovery and computer forensic analysis. The present invention allows a non-technical person such as a non-forensic expert to conduct electronic discovery and thereby obviate the need for an expert in many situations. The present invention allows for electronic discovery in a forensically sound manner. The present invention also concerns a business method for electronic discovery involving a software program and a command server for generating expanded functionality. The client software may be distributed at minimal or no cost, preferably as a CD. Using the client software, a user boots a target machine to determine whether a target machine contains data of interest. The client software will, however, only display limited data such as file information, date, last modified, and file size. To access and examine the actual underlying data, the user must obtain additional functionality, e.g.

Abstract: A computer readable medium including executable instructions to analyze radio frequency (RF) tag information includes executable instruction to access cross-enterprise RF tag information, identify a product transition based upon the cross-enterprise RF tag information, and define a new product path based upon the product transition, where the new product path defines product pedigree information. Additional executable instructions authenticate a user, secure product information, supply product pedigree information corresponding to the product information, and verify the pedigree of the product based upon the product pedigree information.

Abstract: A computer readable medium including executable instructions to analyze radio frequency (RF) tag information includes executable instruction to access cross-enterprise RF tag information, identify a product transition based upon the cross-enterprise RF tag information, and define a new product path based upon the product transition, where the new product path defines product pedigree information. Additional executable instructions authenticate a user, secure product information, supply product pedigree information corresponding to the product information, and verify the pedigree of the product based upon the product pedigree information.

Abstract: Disclosed is a method, system and service for developing an end-to-end process for managing acquisitions including, developing strategies and identify an appropriate company for acquisition, managing a transaction and negotiating a deal, integrating an acquired acquisition, and tracking performance against defined business case targets and milestones.

Abstract: Hot air blown past memory modules under test in a heat chamber is improved. Hot air entering the chamber from an inlet pipe is split by a manifold and deflectors. Holes in the manifold allow for a relatively even air distribution within the chamber, minimizing temperature variations. Return air is collected by a heat-chamber bottom cover into a return pipe. A heating unit re-heats the return air and blows it into the inlet pipe. One side of the heat chamber is an insulated backplane. Memory modules are inserted into sockets on module motherboards, which are inserted into motherboard sockets on the backplane. On the other side of the backplane, card sockets receive pattern-generator cards outside the heat chamber but electrically connected to the module motherboards through the backplane. The pattern-generator cards exercise the memory modules. The pattern-generator cards are cooled while memory modules in the heat chamber are heated.