Patents by Inventor David SUNG

David SUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11769048
    Abstract: In an example embodiment, a single machine learned model that allows for ranking of entities across all of the different combinations of node types and edge types is provided. The solution calibrates the scores from Edge-FPR models to a single scale. Additionally, the solution may utilize a per-edge type multiplicative factor dictated by the true importance of an edge type, which is learned through a counterfactual experimentation process. The solution may additionally optimize on a single, common downstream metric, specifically downstream interactions that can be compared against each other across all combinations of node types and edge types.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: September 26, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Parag Agrawal, Ankan Saha, Yafei Wang, Yan Wang, Eric Lawrence, Ashwin Narasimha Murthy, Aastha Nigam, Bohong Zhao, Albert Lingfeng Cui, David Sung, Aastha Jain, Abdulla Mohammad Al-Qawasmeh
  • Patent number: 11715639
    Abstract: A method of manufacturing a semiconductor structure includes depositing a silicon layer over a substrate, removing a portion of the silicon layer to form a gate stack, and performing a hydrogen treatment on the gate stack to repair a plurality of voids in the stack structure.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: August 1, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuan-Chun Sie, Po-Yi Tseng, Chien-Hao Chen, Ching-Lun Lai, David Sung, Ming-Feng Hsieh, Yi-Chi Huang
  • Publication number: 20220083853
    Abstract: In an example embodiment, a single machine learned model that allows for ranking of entities across all of the different combinations of node types and edge types is provided. The solution calibrates the scores from Edge-FPR models to a single scale. Additionally, the solution may utilize a per-edge type multiplicative factor dictated by the true importance of an edge type, which is learned through a counterfactual experimentation process. The solution may additionally optimize on a single, common downstream metric, specifically downstream interactions that can be compared against each other across all combinations of node types and edge types.
    Type: Application
    Filed: September 15, 2020
    Publication date: March 17, 2022
    Inventors: Parag Agrawal, Ankan Saha, Yafei Wang, Yan Wang, Eric Lawrence, Ashwin Narasimha Murthy, Aastha Nigam, Bohong Zhao, Albert Lingfeng Cui, David Sung, Aastha Jain, Abdulla Mohammad Al-Qawasmeh
  • Publication number: 20180151372
    Abstract: A method of manufacturing a semiconductor structure includes depositing a silicon layer over a substrate, removing a portion of the silicon layer to form a gate stack, and performing a hydrogen treatment on the gate stack to repair a plurality of voids in the stack structure.
    Type: Application
    Filed: September 12, 2017
    Publication date: May 31, 2018
    Inventors: Yuan-Chun SIE, Po-Yi TSENG, Chien-Hao CHEN, Ching-Lun LAI, David SUNG, Ming-Feng HSIEH, Yi-Chi HUANG