Abstract: A flash memory comprises an address bus, a data bus, control lines, and an array of addressable nonvolatile memory cells, connected to the address bus and the data bus. A latch, activated by control signals, stores signals supplied from the address bus or the data bus. A decoder decodes the signal stored in the latch, and in response to a first signal decoded for partitioning the array of memory cells into a plurality of first sectors each having a first size, and in response to a second signal decoded for partitioning the array of memory cells into a plurality of second sectors each of a second size, different from the first size. A control circuitry controls the erasure of a first or a second sector of the memory array in response to the first or second signal decoded.

Abstract: A circuit for generating a time base signal from a power line signal produced by an alternating current (AC) power source. The circuit sets the output of a latch to a first state when a positive peak of the power line signal is detected, and sets the output of the latch to a second state when a negative peak is detected. Peaks are detected based upon comparisons between the power line signal and a reference voltage. A reference circuit derives the reference voltage from the power line signal using an AC-to-DC converter to generate a peak voltage signal from the power line signal and a reference generator to generate a reference voltage based upon the peak voltage signal. Positive and negative peaks are detected using positive and negative peak detectors.