Abstract: A method of generating a microfluidic ejection chip is provided. The method includes creating an opening in a silicon substrate through multiple iterations of a deep reactive ion etching process, forming a passivation layer over any exposed portion of silicon at the opening following each iteration of the deep reactive ion etching of the silicon substrate, and not removing the passivation layer at a conclusion of the etching of the silicon substrate to define a fluid passageway at the opening in the silicon substrate, such that the passivation layer is permanent on the silicon substrate at the opening.

Abstract: In at least one embodiment there is provided a method for managing bulk capacitance of a power supply system. The method includes precharging first and second bulk capacitors of the power supply system to approximately a first output voltage level and a second output voltage level, respectively; receiving a first command signal to generate, by the power supply, the first output voltage level; coupling the first bulk capacitance to load circuitry coupled to the power supply; receiving a second command signal to generate, by the power supply, the second output voltage level; and coupling the second bulk capacitance to the load circuitry coupled to the power supply.

Abstract: In at least one embodiment there is provided a method for managing bulk capacitance of a power supply system. The method includes precharging first and second bulk capacitors of the power supply system to approximately a first output voltage level and a second output voltage level, respectively; receiving a first command signal to generate, by the power supply, the first output voltage level; coupling the first bulk capacitance to load circuitry coupled to the power supply; receiving a second command signal to generate, by the power supply, the second output voltage level; and coupling the second bulk capacitance to the load circuitry coupled to the power supply.