Abstract: Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.

Abstract: A method and device are provided for multilingual speech recognition. In one example, a speech recognition method includes receiving a multilingual input speech signal, extracting a first phoneme sequence from the multilingual input speech signal, determining a first language likelihood score indicating a likelihood that the first phoneme sequence is identified in a first language dictionary, determining a second language likelihood score indicating a likelihood that the first phoneme sequence is identified in a second language dictionary, generating a query result responsive to the first and second language likelihood scores, and outputting the query result.