Abstract: A multiprocessing computer system and method providing multiplexed address and data paths from multiple CPUs to a single storage device. These paths are controlled by an arbitration circuit which allows one CPU to always have the highest priority. The primary CPU may or may not be the highest priority CPU in the arbitration scheme. The arbitration circuit is combined with a controlling mechanism which interfaces to the memory device. This controller operates at a clock rate fast enough to allow the highest priority CPU to access the memory at it's highest data rate and, yet, guarantees a maximum idle period for the lower priority CPU to wait for it's interleaved memory access to complete. A single memory device provides cost and space savings. A controller is responsive to these processors to multiplex their information signals for selectively conveying information present at their address and data ports.

Abstract: An interface between the host CPU and the programmably memory, providing an address, data and read/write control signals to create a non-volatile sector within the programmable memory. In an embodiment when the system reset is de-asserted immediately after power-on, the size of the protected EEPROM area is sensed on special strapping option pins and automatically configures the non-volatile sector. This allows the size of the protected area to be changed on the manufacturing line as needed for different applications. Once configured to protect a specific size and location in the non-volatile memory, the invention prevents the write control signal to the memory to be asserted when the address of the data access requested by the CPU is in the protected area of the memory. This has the effect of preventing modification of the protected area by a sector modification algorithm.

Abstract: A programmable hardware timer provides a relatively consistently measure of predetermined time intervals over a relatively wide range of performance levels. The programmable hardware timer includes a downcounter, driven by a predetermined clock frequency, that counts a preprogrammed number of preselected time intervals. The time intervals, also programmable, are written to registers which, in turn, are used to control the downcounter such that the zero flag on the downcounter goes active at the predetermined time interval. A second downcounter is used to enable multiples of the predetermined time interval to be selected.

Abstract: A computer system employs a process on warm boot which obviates the need to copy code in non-volatile memory to volatile memory; a normal function in a warm boot process. The computer system checks a warm boot flag which indicates that the code was previously copied on cold boot. By avoiding copying this already copied code and executing directly from the volatile memory considerable time is saved. Since BIOS code is typically on the order of 10K bytes, elimination of the necessity to rewrite BIOS and vectoring directly to BIOS image file in RAM saves on the order of ten thousand clock cycles.

Abstract: In the present invention, a single EEPROM is used to store firmware for the CPU, firmware for the SCP and the system password and other critical system data. Hardware protection is provided that prevents the CPU from accessing the portion of the EEPROM that contains the password or other critical systems data.

Abstract: The invention provides for a CPU in a digital system to control the location of the code being executed by one or more peripheral CPUs when all CPUs share a common memory. This allows the CPU to allocate convenient (e.g., unused) blocks of its address space for the code for the peripheral CPU(s). Additionally, for digital systems in which the peripheral CPU(s) cannot address the full range of the address space of the shared memory that is available to the CPU, the CPU can control the relocation of the block of code for the peripheral CPU(s) (i.e., provide a code paging system).

Abstract: A programmable hardware timer provides a relatively consistently measure of predetermined time intervals over a relatively wide range of performance levels. The programmable hardware timer includes a downcounter, driven by a predetermined clock frequency, that counts a preprogrammed number of preselected time intervals. The time intervals, also programmable, are written to registers which, in turn, are used to control the downcounter such that the zero flag on the downcounter goes active at the predetermined time interval. A second downcounter is used to enable multiples of the predetermined time interval to be selected.

Abstract: The invention provides a simple I/O port which can be used to support a variety of system functions such as a revision, configuration or identification register. This port is provided with a means to be programmable once, upon system power-up so that changes to the port contents are possible, but only under controlled conditions. Once the register has been programmed, it will no longer respond to writes.

Abstract: The invention provides a simple I/O port which can be used to support a variety of system functions such as a revision, configuration or identification register. This port is provided with a means to be programmable once, upon system power-up so that changes to the port contents are possible, but only under controlled conditions. Once the register has been programmed, it will no longer respond to writes.

Abstract: The invention provides a simple I/O port which can be used to support a variety of system functions such as a revision, configuration or identification register. This port is provided with a means to be programmable once, upon system power-up so that changes to the port contents are possible, but only under controlled conditions. Once the register has been programmed, it will no longer respond to writes.

Abstract: A method and apparatus providing alternate access to standard ports to enable the functionality of such standard ports to be expanded without the need to provide additional software or hardware while obviating the problem that any non-standard commands will be ignored. All standard commands are written to the standard ports. However, any non-standardized commands are written to the standardized ports by way of an alternate access path. In particular, the non-standardized commands are written to an index register and a value register at non-standardized port addresses. The value written to the index register selects one of a predetermined group of index registers, while the value register is used for data for the register selected by the index register. By including standardized port addresses, such as 60H and 64H in the group of index registers, non-standardized commands can be written to these ports by way of the index register to enable non-standardized commands to be assigned to such standardized ports.

Abstract: An apparatus and method for tracking and interception of instructions as they are presented to the memory, selectively passing harmless data to the device and disallowing the sequences which instruct the device to perform harmful functions, such as self-erase. A software trap is provided to be transparent to the operation of the device and the host system, imposing no harmful timing delays or software overhead. Accordingly, the invention allows the use of standard electrically erasable read-only memories in an application which requires that the device be protected from global erasure. A hardware front end intercepts the software command which is used to globally erase the device.