Abstract: An approach is provided in which a multi-core processor's first core determines whether it controls a system frequency that drives a group of cores included in the multi-core processor. When the first core is not controlling the system frequency for the group of cores, the first core uses an internal voltage control module to provide control information to the first core's programmable voltage regulator and, in turn, independently control the first core's voltage level. When the first core is controlling the system frequency, the first core receives voltage control information from pervasive control to control the first core's voltage levels.

Abstract: An approach is provided in which a multi-core processor's first core determines whether it controls a system frequency that drives a group of cores included in the multi-core processor. When the first core is not controlling the system frequency for the group of cores, the first core uses an internal voltage control module to provide control information to the first core's programmable voltage regulator and, in turn, independently control the first core's voltage level. When the first core is controlling the system frequency, the first core receives voltage control information from pervasive control to control the first core's voltage levels.

Abstract: An approach is provided in which a multi-core processor's first core determines whether it controls a system frequency that drives a group of cores included in the multi-core processor. When the first core is not controlling the system frequency for the group of cores, the first core uses an internal voltage control module to provide control information to the first core's programmable voltage regulator and, in turn, independently control the first core's voltage level. When the first core is controlling the system frequency, the first core receives voltage control information from pervasive control to control the first core's voltage levels.

Abstract: An approach is provided in which a multi-core processor's first core determines whether it controls a system frequency that drives a group of cores included in the multi-core processor. When the first core is not controlling the system frequency for the group of cores, the first core uses an internal voltage control module to provide control information to the first core's programmable voltage regulator and, in turn, independently control the first core's voltage level. When the first core is controlling the system frequency, the first core receives voltage control information from pervasive control to control the first core's voltage levels.

Abstract: A circuit for monitoring and controlling a clock signal generated by a clock source in a microprocessor device may include a voltage divider network that provides a plurality of voltages, a selector device that receives the plurality of voltages and provides a scaled supply voltage and a scaled ground voltage from the plurality of voltages, and at least one delay element that receives the scaled supply voltage and the scaled ground voltage and generates a delayed pulse signal by applying a delay to each pulse of the clock signal. The delayed pulse signal may include a delay magnitude that is controllable by the scaled supply voltage and the scaled ground voltage, such that the delayed pulse signal is used to generate a frequency correction signal based on a variation to a supply voltage of the microprocessor. The frequency correction signal may then be applied to the clock source.

Abstract: A digitally-controlled oscillator includes a base frequency generator having an odd number of base inverters connected end-to-end to generate an output signal that oscillates at a predetermined frequency and a frequency-adjusting unit connected to the base frequency generator. The frequency-adjusting unit includes a first string of switchable inverters connected in series with each other, the switchable inverters having sizes that decrease from an input end of the first string to the output end of the first string.

Abstract: A circuit for monitoring and controlling a clock signal generated by a clock source in a microprocessor device may include a voltage divider network that provides a plurality of voltages, a selector device that receives the plurality of voltages and provides a scaled supply voltage and a scaled ground voltage from the plurality of voltages, and at least one delay element that receives the scaled supply voltage and the scaled ground voltage and generates a delayed pulse signal by applying a delay to each pulse of the clock signal. The delayed pulse signal may include a delay magnitude that is controllable by the scaled supply voltage and the scaled ground voltage, such that the delayed pulse signal is used to generate a frequency correction signal based on a variation to a supply voltage of the microprocessor. The frequency correction signal may then be applied to the clock source.

Abstract: A digitally-controlled oscillator includes a base frequency generator having an odd number of base inverters connected end-to-end to generate an output signal that oscillates at a predetermined frequency and a frequency-adjusting unit connected to the base frequency generator. The frequency-adjusting unit includes a first string of switchable inverters connected in series with each other, the switchable inverters having sizes that decrease from an input end of the first string to the output end of the first string.

Abstract: A terminator circuit for connection to a network can be fabricated and used within CMOS-SOI (complementary metal oxide semiconductor—silicon on insulator) for carrying small logic level signals for connecting data from a network's first circuit to a network's second circuit in which a network's input terminal connects a terminator circuit to the network's second circuit to act as a terminator on the data line passing data from said first circuit to said second circuit. The terminator circuit has a reference circuit coupled to a terminal circuit. The reference circuit has SOI devices back to back source coupled CMOS-SOI devices to each other for a tuned center reference voltage node, with their bodies connect to upper and lower level power supplies respectively. An upper level power source is connected to one side of the reference voltage node and a lower reference voltage power source is connected to the other side of the reference voltage node.

Abstract: A terminator circuit for connection to a network can be fabricated and used within CMOS-SOI (complementary metal oxide semiconductor—silicon on insulator) for carrying small logic level signals for connecting data from a network's first circuit to a network's second circuit in which a network's input terminal connects a terminator circuit to the network's second circuit to act as a terminator on the data line passing data from the first circuit to the second circuit. The terminator circuit has a reference circuit coupled to a terminal circuit and to a differential hysteresis receiver. The reference circuit has devices back to back source coupled devices to each other for a tuned center reference voltage node. An upper level power source is connected to one side of the reference voltage node and a lower reference voltage power source is connected to the other side of the reference voltage node.

Abstract: CMOS small signal switchable impedence and voltage adjustable terminator with an integrated hysteresis receiver network for carrying small logic level signals for connecting data from a network's first circuit to a network's second circuit in which a network's input terminal connects a terminator circuit to the network's second circuit to act as a terminator on the data line passing data from said first circuit to said second circuit. The terminator circuit has a reference circuit coupled to a terminal circuit. The reference circuit has devices back to back source coupled devices to each other for a tuned center reference voltage node, with their bodies connect to upper and lower level power supplies respectively. An upper level power source is connected to one side of the reference voltage node and a lower reference voltage power source is connected to the other side of the reference voltage node.

Abstract: A terminator circuit for connection to a network can be fabricated and used within CMOS-SOI (complementary metal oxide semiconductor—silicon on insulator) for carrying small logic level signals for connecting data from a network's first circuit to a network's second circuit in which a network's input terminal connects a terminator circuit to the network's second circuit to act as a terminator on the data line passing data from said first circuit to said second circuit. The terminator circuit has a reference circuit coupled to a terminal circuit. The reference circuit has SOI devices back to back source coupled CMOS-SOI devices to each other for a tuned center reference voltage node, with their bodies connect to upper and lower level power supplies respectively. An upper level power source is connected to one side of the reference voltage node and a lower reference voltage power source is connected to the other side of the reference voltage node.

Abstract: A terminator circuit for connection to a network can be fabricated and used within CMOS-SOI (complementary metal oxide semiconductor—silicon on insulator) for carrying small logic level signals for connecting data from a network's first circuit to a network's second circuit in which a network's input terminal connects a terminator circuit to the network's second circuit to act as a terminator on the data line passing data from said first circuit to said second circuit. The terminator circuit has a reference circuit coupled to a terminal circuit. The reference circuit has SOI devices back to back source coupled CMOS-SOI devices to each other for a tuned center reference voltage node, with their bodies connect to upper and lower level power supplies respectively. An upper level power source is connected to one side of the reference voltage node and a lower reference voltage power source is connected to the other side of the reference voltage node.

Abstract: A CMOS terminator circuit for connection to a network can be fabricated and used within for carrying small logic level signals for connecting data from a network's first circuit to a network's second circuit in which a network's input terminal connects a terminator circuit to the network's second circuit to act as a terminator on the data line passing data from said first circuit to said second circuit. The terminator circuit has a reference circuit coupled to a terminal circuit. The reference circuit has SOI devices back to back source coupled devices to each other for a tuned center reference voltage node, with their bodies connect to upper and lower level power supplies respectively. An upper level power source is connected to one side of the reference voltage node and a lower reference voltage power source is connected to the other side of the reference voltage node.

Abstract: A terminator circuit for connection to a network can be fabricated and used within CMOS (complementary metal oxide semiconductor) for carrying small logic level signals for connecting data from a network's first circuit to a network's second circuit in which a network's input terminal connects a terminator circuit to the network's second circuit to act as a terminator on the data line passing data from said first circuit to said second circuit. The terminator circuit has a reference circuit coupled to a terminal circuit. The reference circuit has SOI devices back to back source coupled CMOS-SOI devices to each other for a tuned center reference voltage node, with their bodies connect to upper and lower level power supplies respectively. An upper level power source is connected to one side of the reference voltage node and a lower reference voltage power source is connected to the other side of the reference voltage node.

Abstract: A terminator circuit for connection to a network can be fabricated and used within CMOS-SOI (complementary metal oxide semiconductor-silicon on insulator) for carrying small logic level signals for connecting data from a network's first circuit to a network's second circuit in which a network's input terminal connects a terminator circuit to the network's second circuit to act as a terminator on the data line passing data from said first circuit to said second circuit. The terminator circuit has a reference circuit coupled to a terminal circuit. The reference circuit has SOI devices back to back source coupled CMOS-SOI devices to each other for a tuned center reference voltage node, with their bodies connect to upper and lower level power supplies respectively. An upper level power source is connected to one side of the reference voltage node and a lower reference voltage power source is connected to the other side of the reference voltage node.

Abstract: A terminator circuit for connection to a network can be fabricated and used within CMOS-SOI (complementary metal oxide semiconductor—silicon on insulator) for carrying small logic level signals for connecting data from a network's first circuit to a network's second circuit in which a network's input terminal connects a terminator circuit to the network's second circuit to act as a terminator on the data line passing data from said first circuit to said second circuit. The terminator circuit has a reference circuit coupled to a terminal circuit. An adjustment section provides an impedance adjustment and adjustment circuits for tuning the center voltage of the incoming voltage swing up and down. A differential receiver has a stable and well centered threshold voltage is coupled to the network input terminal for connecting the network's first circuit to the network's second circuit.

Abstract: A terminator circuit for connection to a network can be fabricated and used within CMOS-SOI (complementary metal oxide semiconductor—silicon on insulator) for carrying smal logic level signals for connecting data from a network's first circuit to a network's second circuit in which a network's input terminal connects a terminator circuit to the network's second circuit to act as a terminator on the data line passing data from said first circuit to said second circuit. The terminator circuit has a reference circuit coupled to a terminal circuit and to a differential hysteresis receiver.

Abstract: A terminator circuit for connection to a network can be fabricated and used within CMOS-SOI (complementary metal oxide semiconductor—silicon on insulator) for carrying small logic level signals for connecting data from a network's first circuit to a network's second circuit in which a network's input terminal connects a terminator circuit to the network's second circuit to act as a terminator on the data line passing data from said first circuit to said second circuit. The terminator circuit has a reference circuit coupled to a terminal circuit. The reference circuit has SOI devices back to back source coupled CMOS-SOI devices to each other for a tuned center reference voltage node, with their bodies connect to upper and lower level power supplies respectively. An upper level power source is connected to one side of the reference voltage node and a lower reference voltage power source is connected to the other side of the reference voltage node.

Abstract: A terminator circuit for connection to a network can be fabricated and used within CMOS-SOI (complementary metal oxide semiconductor—silicon on insulator) for carrying small logic level signals for connecting data from a network's first circuit to a network's second circuit in which a network's input terminal connects a terminator circuit to the network's second circuit to act as a terminator on the data line passing data from said first circuit to said second circuit. The terminator circuit has a reference circuit coupled to a terminal circuit. The reference circuit has SOI devices back to back source coupled CMOS-SOI devices to each other for a tuned center reference voltage node, with their bodies connect to upper and lower level power supplies respectively. An upper level power source is connected to one side of the reference voltage node and a lower reference voltage power source is connected to the other side of the reference voltage node.