Patents by Inventor David T. Powers
David T. Powers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11938862Abstract: A hazard beacon has an interface to a vehicle wiring harness configured to detect that vehicle emergency indicators have been deployed, a plurality of separately strobe capable light segments forming a hazard symbol, and a microcontroller controlling operation of the plurality of separately strobe capable light segments.Type: GrantFiled: October 4, 2021Date of Patent: March 26, 2024Assignee: ESS-Help, Inc.Inventors: John Zachariah Cobb, Daniel Anthony Tucker, David M. Tucker, Stephen T. Powers, Austin Reece Tucker, Kenneth E. Wagner, Mike Incorvaia
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Publication number: 20240067087Abstract: A microprocessor in a vehicle receives an indication of a hazard event associated with the vehicle and transmits and alerts to a safety alert system. The safety alert system may forward the alert to additional vehicles based upon a number of factors.Type: ApplicationFiled: August 28, 2023Publication date: February 29, 2024Inventors: DAVID M. TUCKER, STEPHEN T. POWERS, MIKE INCORVAIA, AUSTIN REECE TUCKER
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Patent number: 5758054Abstract: A method and apparatus are provided for detecting and correcting various data errors that may arise in a mass data storage apparatus comprising a set of physical mass storage devices operating as one or more larger logical mass storage devices. More particularly, there is provided a method and apparatus for determining, on restoration of power to a device set, whether or not a write operation was interrupted when power was removed, and for reconstructing any data that may be inconsistent because of the removal of power.Type: GrantFiled: December 11, 1995Date of Patent: May 26, 1998Assignee: EMC CorporationInventors: Randy H. Katz, David T. Powers, David H. Jaffe, Joseph S. Glider, Thomas E. Idleman
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Patent number: 5651110Abstract: A method and apparatus for controlling data flow between a computer and a group of memory devices arranged in a particular logical configuration. The system includes a group of first level controllers and a group of second level controllers. The first level controllers and the second level controllers work together such that if one of the second level controllers fails, the routing between the first level controllers and the memory devices is switched to a properly functioning second level controller without the need to involve the computer in the rerouting process. The logical configuration of the memory devices remains constant. The invention also includes switching circuitry which permits a functioning second level controller to assume control of a group of memory devices formerly primarily controlled by the failed second level controller.Type: GrantFiled: April 12, 1995Date of Patent: July 22, 1997Assignee: Micro Technology Corp.Inventors: David T. Powers, David H. Jaffe, Larry P. Henson, Hoke S. Johnson, III, Joseph S. Glider, Thomas E. Idleman
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Patent number: 5475697Abstract: A method and apparatus are provided for detecting and correcting various data errors that may arise in a mass data storage apparatus comprising a set of physical mass storage devices operating as one or more larger logical mass storage devices. More particularly, there is provided a method and apparatus for determining, on restoration of power to a device set, whether or not a write operation was interrupted when power was removed, and for reconstructing any data that may be inconsistent because of the removal of power.Type: GrantFiled: April 6, 1994Date of Patent: December 12, 1995Assignee: MTI Technology CorporationInventors: Randy H. Katz, David T. Powers, David H. Jaffe, Joseph Glider, Thomas E. Idleman
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Patent number: 5469453Abstract: Methods and apparatus are provided for detecting and correcting various data errors that may arise in a mass data storage apparatus comprising a set of physical mass storage devices operating as one or more larger logical mass storage devices. A method and apparatus is provided for detecting and reconstructing incorrectly routed data. A method and apparatus is also provided for detecting when one or more physical devices fails to write a block of data, and for reconstructing lost data.Type: GrantFiled: February 21, 1995Date of Patent: November 21, 1995Assignee: MTI Technology CorporationInventors: Joseph S. Glider, David T. Powers, Thomas E. Idleman
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Patent number: 5325497Abstract: A method and apparatus for identifying each of the members of a set of physical mass storage devices acting as one logical mass storage device are provided. Each physical mass storage device is assigned a membership signature identifying it as a valid member of the set. Whenever a member of a set undergoes a change in membership status, the membership signatures of all other devices in the set are changed, so that the member with the changed membership state no longer has a valid signature. When the member is reinstalled, it can be given a new valid signature after it is updated or regenerated.Type: GrantFiled: March 29, 1990Date of Patent: June 28, 1994Assignee: Micro Technology, Inc.Inventors: David H. Jaffe, David T. Powers, Joseph S. Glider, Thomas E. Idleman
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Patent number: 5285451Abstract: A mass memory system for digital computers is disclosed. The system has a plurality of disk drives coupled to a plurality of small buffers. An Error Correction Controller is coupled to a plurality of X-bar switches, the X-bar switches being connected between each disk drive and its buffers. Data is read from and written to the disk drives in parallel and error correction is also performed in parallel. The X-bar switches are used to couple and decouple functional and nonfunctional disk drives to the system as necessary. Likewise, the buffers can be disconnected from the system should they fail. The parallel architecture, combined with a Reed-Solomon error detection and correction scheme and X-bar switches allows the system to tolerate and correct any two failed drives, allowing for high fault-tolerance operation.Type: GrantFiled: July 15, 1992Date of Patent: February 8, 1994Assignee: Micro Technology, Inc.Inventors: Larry P. Henson, Kumar Gajjar, David T. Powers, Thomas E. Idleman
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Patent number: 5274645Abstract: A method and apparatus for controlling data flow between a computer and a group of memory devices arranged in a particular logical configuration. The system includes a group of first level controllers and a group of second level controllers. The first level controllers and the second level controllers work together such that if one of the second level controllers fails, the routing between the first level controllers and the memory devices is switched to a properly functioning second level controller without the need to involve the computer in the rerouting process. The logical configuration of the memory devices remains constant. The invention also includes switching circuitry which permits a functioning second level controller to assume control of a group of memory devices formerly primarily controlled by the failed second level controller. In addition, the invention provides error check and correction as well as mass storage device configuration circuitry.Type: GrantFiled: April 23, 1992Date of Patent: December 28, 1993Assignee: Micro Technology, Inc.Inventors: Thomas E. Idleman, Robert S. Koontz, David T. Powers, David H. Jaffe, Larry P. Henson, Joseph S. Glider, Kumar Gajjar
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Patent number: 5233618Abstract: Methods and apparatus are provided for detecting and correcting various data errors that may arise in a mass data storage apparatus comprising a set of physical mass storage devices operating as one or more larger logical mass storage devices. A method and apparatus is provided for detecting and reconstructing incorrectly routed data. A method and apparatus is also provided for detecting when one or more physical devices fails to write a block of data, and for reconstructing lost data.Type: GrantFiled: March 2, 1990Date of Patent: August 3, 1993Assignee: Micro Technology, Inc.Inventors: Joseph S. Glider, David T. Powers, Thomas E. Idleman
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Patent number: 5212785Abstract: A method and apparatus for controlling data flow between a computer and a group of memory devices arranged in a particular logical configuration. The system includes a group of first level controllers and a group of second level controllers. The first level controllers and the second level controllers work together such that if one of the second level controllers fails, the routing between the first level controllers and the memory devices is switched to a properly functioning second level controller without the need to involve the computer in the rerouting process. The logical configuration of the memory devices remains constant. The invention also includes switching circuitry which permits a functioning second level controller to assume control of a group of memory devices formerly primarily controlled by the failed second level controller.Type: GrantFiled: April 6, 1990Date of Patent: May 18, 1993Assignee: Micro Technology, Inc.Inventors: David T. Powers, David H. Jaffe, Larry P. Henson, Hoke S. Johnson III, Joseph S. Glider, Thomas E. Idleman
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Patent number: 5195100Abstract: A method and apparatus are provided for detecting and correcting various data errors that may arise in a mass data storage apparatus comprising a set of physical mass storage devices operating as one or more larger logical mass storage devices. More particularly, there is provided a method and apparatus for determining, on restoration of power to a device set, whether or not a write operation was interrupted when power was removed, and for reconstructing any data that may be inconsistent because of the removal of power.Type: GrantFiled: March 2, 1990Date of Patent: March 16, 1993Assignee: Micro Technology, Inc.Inventors: Randy H. Katz, David T. Powers, David H. Jaffe, Joseph S. Glider, Thomas E. Idleman
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Patent number: 5166939Abstract: A mass storage apparatus, made up of a plurality of physical storage devices, which is capable of providing both high bandwidth and high operation rate, as necessary, along with high reliability, is provided. The device set is divided into one or more redundancy groups. Each redundancy group is in turn divided into one or more data groups, each of which may span only a small number of the drives in the redundancy group, providing a high request rate, or which may span a large number of drives, providing high bandwidth.Type: GrantFiled: March 2, 1990Date of Patent: November 24, 1992Assignee: Micro Technology, Inc.Inventors: David H. Jaffe, David T. Powers, Kumar Gajjar, Joseph S. Glider, Thomas E. Idleman
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Patent number: 5140592Abstract: A method and apparatus for controlling data flow between a computer and a group of memory devices arranged in a particular logical configuration. The system includes a group of first level controllers and a group of second level controllers. The first level controllers and the second level controllers work together such that if one of the second level controllers fails, the routing between the first level controllers and the memory devices is switched to a properly functioning second level controller without the need to involve the computer in the rerouting process. The logical configuration of the memory devices remain constant. The invention also includes switching circuitry which permits a functioning second level controller to assume control of a group of memory devices formerly primarily contolled by the failed second level controller. In addition, the invention provides error check and correction as well as mass storage device configuration circuitry.Type: GrantFiled: October 22, 1990Date of Patent: August 18, 1992Assignee: SF2 CorporationInventors: Thomas E. Idleman, Robert S. Koontz, David T. Powers, David H. Jaffe, Larry P. Henson, Joseph S. Glider, Kumar Gajjar
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Patent number: 5134619Abstract: A mass memory system for digital computers is disclosed. The system has a plurality of disk drives coupled to a plurality of small buffers. An Error Correction Controller is coupled to a plurality of X-bar switches, the X-bar switches being connected between each disk drive and its buffers. Data is read from and written to the disk drives in parallel and error correction is also performed in parallel. The X-bar switches are used to couple and decouple functional and nonfunctional disk drives to the system as necessary. Likewise, the buffers can be disconnected from the system should they fail. The parallel architecture, combined with a Reed-Solomon error detection and correction scheme and X-bar switches allows the system to tolerate and correct any two failed drives, allowing for high fault-tolerance operation.Type: GrantFiled: April 6, 1990Date of Patent: July 28, 1992Assignee: SF2 CorporationInventors: Larry P. Henson, Kumar Gajjar, David T. Powers, Thomas E. Idleman