Abstract: Data can be accurately transmitted between two subsystems in a synchronous system even if the clock skew or propagation delay between the two subsystems is greater than one clock cycle time. The source and destination subsystems are initialized to ensure synchronous operation. The source subsystem transmits data and a forwarded clock to the destination subsystem. The forwarded clock is passed through a delay device to introduce a one-half cycle delay into the forwarded clock timing. Data is captured in three state devices arranged in parallel to eliminate minimum delay requirements and to expand data valid time. The captured data is then aligned to the destination subsystem's clock by controlling a multiplexer which selects the proper signal at its input to pass to the input of a second state device coupled to its output. The data selected is then clocked into the second state device under the control of the distination subsystem's clock, thus aligning the received data with the destination subsystem's clock.

Abstract: A VSLI circuit includes a plurality of state device circuits on a VLSI chip. Each of the state device circuits includes a latch and is clocked by a pulse generator circuit which produces narrow pulses that are coupled to the clock input of the latch. The narrow pulses have a pulse width substantially equivalent to the propagation delay through the latch of the state device circuits. By taking advantage of the high correlative percentages of devices on portions of the chip, master-slave flip flops can be implemented using only a single latch with a pulse generator.