Abstract: A method and apparatus for determining the location of a node within a communication system is provided herein. During operation, located nodes (105) having known locations are utilized to locate “blind” nodes (200) whose location is to be determined. More particularly, a blind node (200) wishing to determine its location will measure a plurality of signal strengths between itself and a plurality of located nodes (105). Each located node's signal strength will then be adjusted based on at least one antenna gain pattern. A radio-location algorithm will then be executed on the adjusted signal-strength measurements to determine the nodes location.

Abstract: To enable wireless applications which require the use of location information, a method and apparatus for transmitting location data within an ad-hoc communication system is provided herein. During operation, a portion of a packet payload is used to transmit location coordinate information along with an identifier of location estimation technique utilized for a node, as well as other parameters that may be needed for location estimation. Nodes in the communication system calculate their location coordinates using the said portion of packets received from other nodes in the communication system.

Abstract: A method and apparatus for determining the location of a node within a communication system is provided herein. During operation, reference nodes (105) having known locations are utilized to locate “blind” nodes (104) whose location is to be determined. More particularly, a blind node (104) wishing to determine its location will measure a plurality of path losses between itself and a plurality of reference nodes (105). These reference nodes' locations will then be mathematically weighted by the path loss between these reference nodes (105) and the blind node (104). The location of the blind node (104) is a sum of the mathematically weighted reference nodes' locations.

Abstract: A node (101) using a contention-based access scheme will monitor a channel for a predetermined condition. If the predetermined condition is detected, the node will defect from the contention-based access scheme, where any generated messages will be immediately transmitted. Should a second condition be met, the node will again follow the contention-based access scheme.

Abstract: When a candidate node (104) wishes to join a network (100), network access is either allowed or denied based on the candidate node's physical location. More particularly, a plurality of nodes associated with the network aide in locating the candidate node. Once located, a decision is made to either allow or deny network access based on the candidate node's physical location.

Abstract: A reconfigurable logic signal processor system (RLSP) (100) and method of error checking same in accordance with certain embodiments of the present invention loads configuration data capable of processing an air interface or portion thereof in a wireless system from a configuration storage memory (112) into reconfigurable resources (104), reads back the configuration data from the reconfigurable resources (104), reads expected results from the configuration storage memory (112), and executes a verification algorithm on the configuration data read back from the reconfigurable resources (104). A portion of the reconfigurable resources (104) of the RLSP system (100) may be utilized to implement the error checking upon itself. If an error is found in the configuration data, steps can be taken to activate another base configuration data to implement a functional base air interface in a wireless communication system and request downloading (if available) from the network of the erroneous configuration data.

Abstract: A processor (216) time-shares correlators (206) to process (402) pilot channels for a plurality of branches to derive pilot symbols for each of the plurality of branches before processing control and data channels. The processor and the correlators cooperate to determine (404) from the pilot symbols a timing estimate for each of the plurality of branches. A signal quality estimator (210) determines (406) from the pilot symbols a signal quality for each of the plurality of branches. Subsequently, the processor cooperates with the correlators to process (408) the control and data channels of the plurality of branches, in an order determined by a plurality of branch attributes including at least one of the signal quality and the timing estimate determined for each of the plurality of branches.

Abstract: A direct sequence spread spectrum (DSSS) receiver (100) consistent with certain embodiments has a frequency generator (112) that generates a local oscillator signal without use of a piezoelectric crystal. A frequency converter (108) receives the local oscillator signal and mixes the local oscillator signal with a received DSSS signal to produce a down-converted signal. The received DSSS signal is encoded using a first set of DSSS code. A differential chip detector (116) receives the down-converted signal and converts the down-converted signal to a differentially detected signal. A correlator (120) receives the differentially detected signal and correlates the detected signal with a set of DSSS codes that are time-shifted from the first set of DSSS codes. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

Abstract: A method (500) and system for compensation of frequency offset between a first transceiver (102) and a second transceiver (104) in wireless communication are disclosed. The compensation of the frequency offset between two or more transceivers (102, 104) is achieved using frequency synchronization bursts. These bursts contain information about the frequency offset. The frequency synchronization bursts are transmitted by the first transceiver at a range of frequencies above and below its carrier frequency (502). A second transceiver that receives at least one of these bursts (504) determines the frequency offset (504), and adjusts its frequency to match the frequency of the first transceiver (508). Thereafter, the second transceiver may enter a low power sleep mode (510) in order to reduce its power consumption. The second transceiver returns to active mode (512) just before the start of the transmission of the data packets (514).

Abstract: A reconfigurable logic signal processor system (RLSP) (100) and method of error checking same in accordance with certain embodiments of the present invention loads configuration data capable of processing an air interface or portion thereof in a wireless system from a configuration storage memory (112) into reconfigurable resources (104), reads back the configuration data from the reconfigurable resources (104), reads expected results from the configuration storage memory (112), and executes a verification algorithm on the configuration data read back from the reconfigurable resources (104). A portion of the reconfigurable resources (104) of the RLSP system (100) may be utilized to implement the error checking upon itself. If an error is found in the configuration data, steps can be taken to activate another base configuration data to implement a functional base air interface in a wireless communication system and request downloading (if available) from the network of the erroneous configuration data.

Abstract: A reconfigurable logic signal processor (RLSP) (100) and method of configuring same in accordance with the present invention stores a plurality of configuration files (262, 264, . . . , 266) in a configuration storage memory (212) in compressed form. A portion of the reconfigurable resources (204) of the RLSP (100) are configured as a decompresser to provide for decompression of the compressed configuration files (262, 264, . . . , 266). The reconfigurable resources (204) of the RLSP (100) may be utilized to implement signal processing functions (114) as well as process control processor instructions and/or configuration data (120), such as for example decompression of compressed configuration data. When decompression functions are complete, a non-decompression instruction can be executed using the reconfigurable resources allocated to decompression by reallocation of those resources.

Abstract: A processor (216) time-shares correlators (206) to process (402) pilot channels for a plurality of branches to derive pilot symbols for each of the plurality of branches before processing control and data channels. The processor and the correlators cooperate to determine (404) from the pilot symbols a timing estimate for each of the plurality of branches. A signal quality estimator (210) determines (406) from the pilot symbols a signal quality for each of the plurality of branches. Subsequently, the processor cooperates with the correlators to process (408) the control and data channels of the plurality of branches, in an order determined by a plurality of branch attributes including at least one of the signal quality and the timing estimate determined for each of the plurality of branches.