Abstract: A method for generating a compressed representation of a simulated waveform is disclosed. The method may have the steps of: (a) processing circuit model information, (b) identifying a segment of stable repetition; and (c) generating the compressed representation. Step (a) may generate waveform information representing a simulated waveform occurring in the circuit model. Step (b) may identify the segment in the waveform information. In step (c), the compressed waveform information may define the segment by (i) cycle information representing the waveform cycle and (ii) repetition information representing the stable repetitions of the waveform cycle to form the segment.

Abstract: The invention relates to a method of controlling access to a database of a design. The method may comprise the step of identifying a version of the design by a first identifier, allocating first authorization information to the first identifier, and controlling access to the database. The first authorization information may indicate a permission of one or more users to access information in the database in respect of the first identifier. The access may be controlled in accordance with the first authorization information.

Abstract: An accurate high current mirror circuit produces a mirrored current that matches an input current to produce an accuracy at the output of a subsequent stage of amplification of greater than 0.01%. A plurality of transistor devices are arranged in a symmetrical configuration and divided into two groups. The transistors in each of the two groups are connected in parallel to produce a high mirror current from a high input current. A distribution of a source voltage produces the same source voltage at each of the plurality of transistors. An input current metallization and a mirror current metallization are formed within the symmetrical configuration to have a same value of impedance. A plurality of P-channel transistors within the current mirror circuit control a voltage of a point on the input metallization to be the same as a reference voltage, thus causing the mirror current to be referenced around the reference voltage.

Abstract: The present invention may provide a circuit generally having a plurality of addressable memory cells and an access control circuit. The access control circuit may be configured to intercept an access to a faulty cell of the plurality of addressable memory cells. The access control circuit may be further configured to redirect the access to a spare cell of the plurality of addressable memory cells.

Abstract: An accurate high current mirror circuit produces a mirrored current that matches an input current to produce an accuracy at the output of a subsequent stage of amplification of greater than 0.01%. A plurality of transistor devices are arranged in a symmetrical configuration and divided into two groups. The transistors in each of the two groups are connected in parallel to produce a high mirror current from a high input current. A distribution of a source voltage produces the same source voltage at each of the plurality of transistors. An input current metallization and a mirror current metallization are formed within the symmetrical configuration to have a same value of impedance. A plurality of P-channel transistors within the current mirror circuit control a voltage of a point on the input metallization to be the same as a reference voltage thus causing the mirror current to be referenced around the reference voltage.

Abstract: A method for generating a compressed representation of a simulated waveform is disclosed. The method may have the steps of: (a) processing circuit model information, (b) identifying a segment of stable repetition; and (c) generating the compressed representation. Step (a) may generate waveform information representing a simulated waveform occurring in the circuit model. Step (b) may identify the segment in the waveform information. In step (c), the compressed waveform information may define the segment by (i) cycle information representing the waveform cycle and (ii) repetition information representing the stable repetitions of the waveform cycle to form the segment.

Abstract: The present invention may provide a circuit generally having a plurality of addressable memory cells and an access control circuit. The access control circuit may be configured to intercept an access to a faulty cell of the plurality of addressable memory cells. The access control circuit may be further configured to redirect the access to a spare cell of the plurality of addressable memory cells.

Abstract: A counter stage generally comprises a flip-flop and a reset circuit. The flip-flop may be configured to toggle a flip-flop signal between a first and a second state in response to a count signal applied to a clock input to effect a counting operation. The reset circuit may be configured to reset the counter stage to a predetermined state without changing the state of the flip-flop signal.

Abstract: The invention may relate to a digital to analog converter. The digital to analog converter may comprise a plurality of controllable current sources and a control circuit. The plurality of controllable current sources may include a first and a second controllable current source. Each of the plurality of controllable current sources may be controllable between a first state and a second state. The control circuit may be coupled to the plurality of controllable current sources. The control circuit may be configured to control digital to analog conversion at a sampling interval. The control circuit may be configured to control a first state transition of the first controllable current source at a timing in the sampling interval different from a second state transition of the second controllable current source.

Abstract: The present invention may relate to a digital to analog converter for converting a digital signal to an analog signal. The digital to analog converter may comprise decoder logic, an array of clocked sub-circuits, a clock generator and a clock signal controller. The decoder logic may be configured to decode the digital signal to a plurality of control signals for controlling generation of the analog signal. The array of clocked sub-circuits may be configured to receive the control signals. The clock generator may be configured to generate a clock signal for clocking the sub-circuits. The clock signal controller may be configured to inhibit application of the clock signal to one or more of the sub-circuits.

Abstract: The invention relates to a method of controlling access to a database of a design. The method may comprise the step of identifying a version of the design by a first identifier, allocating first authorization information to the first identifier, and controlling access to the database. The first authorization information may indicate a permission of one or more users to access information in the database in respect of the first identifier. The access may be controlled in accordance with the first authorization information.

Abstract: A counter stage generally comprises a flip-flop and a reset circuit. The flip-flop may be configured to toggle a flip-flop signal between a first and a second state in response to a count signal applied to a clock input to effect a counting operation. The reset circuit may be configured to reset the counter stage to a predetermined state without changing the state of the flip-flop signal.