Abstract: The present invention relates to a test for current leakage of driver/receiver stages, and in particular for bi-directional input/output stages (10) of a semiconductor chip. Two dedicated support transistor devices (56, 58) are added into the prior art switching scheme, together with a simple control logic (48, 50, 52, 60, 62, 64) for selectively controlling the two dedicated support transistor devices according to a predetermined test scheme. An on-chip self-test feature provides valid voltage levels which are convertible by the receiver (24) to predictable logic states at the evaluation line RDATA. The test can be performed autonomously on the chip without the requirement for an external test device.

Abstract: The present invention relates to a method and system for full parametric testing of the drive and receive capability of bi-directional driver/receiver-stages, and in particular of bi-directional input/output-stages of a semiconductor chip. Electrical properties, as for example DC-resistance, AC-impedance of a driver stage are tested by at least one test load implemented on the chip itself which causes a characteristic voltage drop usable for test evaluation. Advantageously, the output stage devices of P-type (50, 52) and N-type (54, 56), respectively, are split into at least two sub-devices P1, P2 and N1, N2, and are controlled separately by a control logic (60, 62, 64, 70, 72, 74). Then, for example N2 is used for testing the P device, and P2 is used for testing the N-device. Thus, devices already present on the chip are re-used for test purposes, which makes off-chip testing unnecessary.

Abstract: An ESD clamping circuit arranged in a darlington configuration and constructed from SiGe or similar type material. The ESD clamping circuit includes additional level shifting circuitry in series with either the trigger or clamping device or both, thus allowing non-native voltages that exceed the BVCEO of the trigger and/or clamp devices.

Abstract: An ESD clamping circuit arranged in a darlington configuration and constructed from SiGe or similar type material. The ESD clamping circuit includes additional level shifting circuitry in series with either the trigger or clamping device or both, thus allowing non-native voltages that exceed the BVCEO of the trigger and/or clamp devices.

Abstract: A SiGe ESD power clamp in a Darlington type configuration where the trigger device has a collector-to-emitter breakdown voltage (BVCEO) that is lower than that of the clamping device, and a frequency cutoff that is higher than that of the clamping device.

Abstract: The present invention relates to a test for current leakage of driver/receiver stages, and in particular for bi-directional input/output stages (10) of a semiconductor chip. Two dedicated support transistor devices (56, 58) are added into the prior art switching scheme, together with a simple control logic (48, 50, 52, 60, 62, 64) for selectively controlling the two dedicated support transistor devices according to a predetermined test scheme. An on-chip self-test feature provides valid voltage levels which are convertible by the receiver (24) to predictable logic states at the evaluation line RDATA. The test can be performed autonomously on the chip without the requirement for an external test device.

Abstract: The present invention relates to a method and system for full parametric testing of the drive and receive capability of bi-directional driver/receiver-stages, and in particular of bi-directional input/output-stages of a semiconductor chip. Electrical properties, as for example DC-resistance, AC-impedance of a driver stage are tested by at least one test load implemented on the chip itself which causes a characteristic voltage drop usable for test evaluation. Advantageously, the output stage devices of P-type(50, 52) and N-type(54,56), respectively, are split into at least two sub-devices P1, P2 and N1, N2, and are controlled separately by a control logic (60,62,64,70,72,74). Then, for example N2 is used for testing the P device, and P2 is used for testing the N-device. Thus, devices already present on the chip are re-used for test purposes, which makes off-chip testing unnecessary.

Abstract: An active clamp circuit for digital circuits includes a first MOSFET serially connected between an upper power supply voltage and an input terminal to be clamped, and a second MOSFET serially connected between a lower voltage power supply and the input terminal. The voltages at the gates of the first and second MOSFETs are held at constant first and second reference voltages by a reference circuit and the first reference voltage at the gate of the first MOSFET is less than the second reference voltage at the gate of the second MOSFET. The first and second reference voltages can be changed by connecting the reference circuit to power supply voltages other than the power supply voltages to which the first and second MOSFETs are connected. The reference voltages can also be varied by adding stages of transistors which act as resistors in parallel to the reference circuit. When the first reference voltage is to be varied, it is recommended that the transistors of opposite type be biased independently.

Abstract: Data transmission arrangement for transmitting data between integrated circuit chips in a computer comprises a driver circuit having inputs connected to two discrete data bits. The driver circuit converts the states of the two data bits to one of four possible output voltage levels on each of two data transmission conductors. A receiver circuit connected to the data transmission conductors converge the multi-level signals on the pair of transmission conductors into binary output signals for use in a receiving circuit chip. The driver circuit and receiver circuit are balanced circuits and symmetrically arranged such that essentially the same magnitude of current is drawn from the power bus independent of the value of the signal being transmitted, thereby eliminating Delta-I noise typically occurring on a power bus when binary data is transmitted.

Abstract: Data transmission arrangement for transmitting data between integrated circuit chips in a computer comprises a driver circuit having inputs connected to two discrete data bits. The driver circuit converts the states of the two data bits to one of four possible output voltage levels on each of two data transmission conductors. A receiver circuit connected to the data transmission conductors converge the multi-level signals on the pair of transmission conductors into binary output signals for use in a receiving circuit chip. The driver circuit and receiver circuit are balanced circuits and symmetrically arranged such that essentially the same magnitude of current is drawn from the power bus independent of the value of the signal being transmitted, thereby eliminating Delta-I noise typically occurring on a power bus when binary data is transmitted.

Abstract: Data transmission arrangement for transmitting data between integrated circuit chips in a computer comprises a driver circuit having inputs connected to two discrete data bits. The driver circuit converts the states of the two data bits to one of four possible output voltage levels on each of two data transmission conductors. A receiver circuit connected to the data transmission conductors converge the multi-level signals on the pair of transmission conductors into binary output signals for use in a receiving circuit chip. The driver circuit and receiver circuit are balanced circuits and symmetrically arranged such that essentially the same magnitude of current is drawn from the power bus independent of the value of the signal being transmitted, thereby eliminating Delta-I noise typically occurring on a power bus when binary data is transmitted.