Abstract: A jig boring head, having a holder for holding a cutting bit, mounted to a spindle on a jig boring machine in a two-piece collar on the spindle, with the tool bit holder securely connected to the collar and slidably adjustable in a direction radial to the spindle, so that a simple, easily implemented method for radial cutting with a jig boring machine is realized.

Abstract: A caliper of a type used in measurements in which the invention comprises including offset measurement jaws deployed at an angle to the main plane of said caliper for measuring dimensions offset from the main plane of said caliper. Said caliper may also include means for measuring both internal dimensions and external dimensions, and may further include a readout, such as digital or analog readout means.

Abstract: A machine tool bit holder providing a stable connection between a machine and a tool bit being used to perform machining operations on a work piece. The holder for the tool bit is of simple construction and has a large contact area relative to a tool bit size and a holder size between the holder and the tool bit, and the holder is configured so that the tool bit can be easily mounted into and dismounted from the holder. The holder allows different shapes or configurations of tool bits, such as an angle between the holder and the tool bit, and tool bits that are substantially rectangular as well as substantially round in cross-section.

Abstract: Delay analysis in logic simulation is enhanced by providing, in a simulation model of a logic circuit, a timing delay tag on each circuit path connecting the output of a first with the input of the second circuit element. Each circuit leg is given a delay value and a clock phase tag providing information about how the delay value is clocked. The clock phase tags correspond to respective phases of a multi-phase circuit clock and relate the delay values to particular clock phases. The phase tag also indicates whether the signal on the data path is triggered by the rising or falling edge of the specified clock phase. At circuit nodes, clock phase tags are concatenated. Thus, if a clocked circuit element responds to an input signal which is a composite of several upstream output signals, the concatenated clock phase tags and delay values can be analyzed to determine if a timing adjustment is required. The information further supports the automatic adjustment of delay value, if needed.