Abstract: An improved frequency detector circuit and method is disclosed for frequency acquisition. The frequency detector is particularly useful as part of a frequency loop in a standard two loop clock and data recovery (CDR) circuit because, for among other reasons, the frequency detector is not limited in frequency range. Typically a CDR circuit includes a phase loop and a frequency loop. The frequency loop includes an improved frequency detector which can be simplified as having two parts; a frequency too low detector (FTLD) and a dynamic leakage circuit (DLC). The FTLD monitors the incoming NRZ data and the VCO frequency looking for a rising edge of the VCO between two edges of the data. In one embodiment, the FTLD includes one or more flip-flops to detect the rise and fall of the data and to count the data and clock edges. The DLC is essentially a too high detector and includes a double edge sampler. The DLC monitors the beat frequency between the incoming NRZ data and the VCO.