Abstract: A logic processing device, containing an application specific integrated circuit (“ASIC”) and field programmable gate array (“FPGA”), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and configurable logic circuit (“CLC”) wherein the CLC can be an FPGA. While ASIC is able to perform a specific function in accordance with an ASIC clock domain, the CLC is capable of performing a programmable logic function in accordance with an FPGA clock domain. The phase adjustment circuit is used to automatically facilitate a communication between the ASIC and the CLC in accordance with the ASIC clock domain and the FPGA clock domain.

Abstract: A logic processing device, containing an application specific integrated circuit (“ASIC”) and field programmable gate array (“FPGA”), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and configurable logic circuit (“CLC”) wherein the CLC can be an FPGA. While ASIC is able to perform a specific function in accordance with an ASIC clock domain, the CLC is capable of performing a programmable logic function in accordance with an FPGA clock domain. The phase adjustment circuit is used to automatically facilitate a communication between the ASIC and the CLC in accordance with the ASIC clock domain and the FPGA clock domain.

Abstract: The technology disclosed relates to a platform for ultra-fast, ad-hoc data exploration and faceted navigation on integrated, heterogeneous data sets. The disclosed apparatus and methods for deep linking and state preservation via a URL make it possible to share live data as rendered on a live dashboard, without saving a new state on a server every time data and dashboard elements are updated.

Abstract: A logic processing device, containing an application specific integrated circuit (“ASIC”) and field programmable gate array (“FPGA”), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and configurable logic circuit (“CLC”) wherein the CLC can be an FPGA. While ASIC is able to perform a specific function in accordance with an ASIC clock domain, the CLC is capable of performing a programmable logic function in accordance with an FPGA clock domain. The phase adjustment circuit is used to automatically facilitate a communication between the ASIC and the CLC in accordance with the ASIC clock domain and the FPGA clock domain.

Abstract: IP applications may be hosted on processors other than the processor on which their associated routing entity is hosted by causing the routing context to be extended to the new processor and causing IP termination to occur at the new processor. Applications may define policies specifying packet attributes and actions to be taken on matching packets, so that packets matching the policy may be directed to a processor hosting the application rather than a processor hosting the routing entity. A steering policy manager may be implemented to receive policies from the applications, verify the policy format and uniqueness vis-à-vis previously implemented policies, and implement the policies by passing the policies to one or more steering policy agents. Filters may be programmed into the data plane or the control plane to cause IP termination to occur on the processor hosting the application.

Abstract: IP applications may be hosted on processors other than the processor on which their associated routing entity is hosted by causing the routing context to be extended to the new processor and causing IP termination to occur at the new processor. Applications may define policies specifying packet attributes and actions to be taken on matching packets, so that packets matching the policy may be directed to a processor hosting the application rather than a processor hosting the routing entity. A steering policy manager may be implemented to receive policies from the applications, verify the policy format and uniqueness vis-à-vis previously implemented policies, and implement the policies by passing the policies to one or more steering policy agents. Filters may be programmed into the data plane or the control plane to cause IP termination to occur on the processor hosting the application.

Abstract: OAM may be implemented at an intermediate node on a PBT trunk in an Ethernet network by causing OAM frames to be addressed to the PBT trunk endpoint but causing the OAM frames to carry an indicia (Ether-type, OpCode, TLV value or combination of these and other fields) that the OAM frames are intended to be used for intermediate node OAM functions. The Ether-type, OpCode, and TLV values may be standardized values, or vendor specific values such as OpCode=51 or TLV=31 may be used. Addressing the OAM frames to the PBT trunk end point enables the OAM frames to follow the PBT trunk through the network. The OAM indicia signals to the intermediate nodes that the OAM frames are intended to be used to perform an intermediate node OAM function. The OAM frames may contain reverse trunk information to prevent the intermediate nodes from being required to store correlation between forward and reverse PBT trunks.

Abstract: A method and system for providing a disk drive pivot assembly is disclosed. The method and system include providing a sleeve, a shaft, and a solid lubrication. The sleeve includes a sleeve bearing surface that defines at least a portion of an aperture within the sleeve. The shaft has a shaft bearing surface and is rotatable with respect to the sleeve. The shaft bearing surface abuts the sleeve bearing surface. The solid lubrication resides between the shaft bearing surface and the sleeve bearing surface.

Abstract: A method and system for programming a magnetic memory including a plurality of magnetic elements is disclosed. The method and system include sensing a temperature of the magnetic memory and providing an indication of the temperature of the magnetic memory. The method and system also include providing a current that is based on the indication of temperature of the magnetic memory. The current is temperature dependent and can be used in programming at least a portion of the magnetic elements without the addition of a separately generated current. In addition, the method and system include carrying for at least a portion of the plurality of magnetic elements. The temperature is preferably sensed by at least one temperature sensor, while the current is preferably provided by a current source coupled with the temperature sensor(s).

Abstract: A method and system for providing and using a magnetic memory are disclosed. The method and system include providing a plurality of magnetic memory cells, at least a first write line, and at least a second write line. Each of the magnetic memory cells includes a magnetic element having a top and a bottom. The first write line(s) are connected to the bottom of magnetic element of the first portion of the plurality of magnetic memory cells. The second write line(s) reside above the top of the magnetic element of each of a second portion of the magnetic memory cells. The second write line(s) are electrically insulated from the magnetic element of each of the second portion of the plurality of magnetic memory cells.

Abstract: A method and system for providing a magnetic memory are disclosed. The method and system include providing a plurality of magnetic memory cells and at least one programmable current source. Each of the plurality of magnetic memory cells includes a first magnetic element. The programmable current source(s) are for programming a portion of the plurality of magnetic memory cells. Each of the programmable current source(s) includes a controller and a current source coupled to the controller. The controller is for determining a current provided by the current source and includes at least a second magnetic element. The second magnetic element(s) are substantially the same as the first magnetic element. The controller determines the current provided by the current source based on the at least the second magnetic element.

Abstract: A method and system for providing a magnetic memory is disclosed. The method and system include providing a plurality of magnetic elements and a plurality of reference layers. Each of the magnetic elements includes a free layer and a spacer layer. Each of the reference layers is coupled with a corresponding portion of the magnetic elements. The reference layers are ferromagnetic. A portion of each reference layer functions as at least a portion of a pinned layer for each of the corresponding portion of the magnetic elements. The portion of each of the plurality of reference layers also functions as a write line for the corresponding portion of the plurality of magnetic elements. The spacer layer resides between the free layer of each of the plurality of magnetic elements and the reference layer.

Abstract: A method and system for providing and using a magnetic random access memory (MRAM) array are disclosed. The method and system include providing magnetic storage cells, global word lines and global word line segments, of global bit lines and bit line segments, and selection devices. Each word line segment is coupled with at least one global word line such that the word line segments are selectable. Each word line segment is also coupled to a portion of the magnetic storage cells. Each bit line segment is coupled with at least one global bit line such the bit line segments are selectable. Each bit line segment resides in proximity to and is used to write to a portion of the magnetic storage cells. The bit line segments and the word line segments are coupled with and selectable using the plurality of selection devices.

Abstract: A method and system for providing magnetic memory are disclosed. The method and system include providing a plurality of magnetic memory elements and providing at least one wrapped write line. Each wrapped write line includes a bottom write line and a top write line electrically connected to the bottom write line. The bottom write line resides below a portion of the plurality of magnetic elements, while the top write resides above the portion of the plurality of magnetic elements. The bottom write line carries a first current in a first direction, while the top write line carries a second current in a second direction opposite to the first direction.

Abstract: A method and system for programming a magnetic memory including a plurality of magnetic elements is disclosed. The method and system include sensing a temperature of the magnetic memory and providing an indication of the temperature of the magnetic memory. The method and system also include providing a current that is based on the indication of temperature of the magnetic memory. The current is temperature dependent and can be used in programming at least a portion of the magnetic elements without the addition of a separately generated current. In addition, the method and system include carrying for at least a portion of the plurality of magnetic elements. The temperature is preferably sensed by at least one temperature sensor, while the current is preferably provided by a current source coupled with the temperature sensor(s).

Abstract: A method and system for providing and using a magnetic memory are disclosed. The method and system include providing a plurality of magnetic memory cells and providing at least one magnetic write line coupled with the plurality of magnetic memory cells. Each of the magnetic memory cells includes a magnetic element having a data storage layer. The data storage layer stores data magnetically. The magnetic write line(s) are magnetostatically coupled with at least the data storage layer of the magnetic element of the corresponding magnetic memory cells. Consequently, flux closure is substantially achieved for the data storage layer of each of the plurality of magnetic memory cells.

Abstract: A method and system for providing and using a magnetic random access memory are disclosed. The method and system include providing a plurality of magnetic memory cells, a first plurality of write lines, and a second plurality of write lines. The first plurality of write lines is a plurality of magnetic write lines. At least one of the plurality of magnetic lines and at least one of the second plurality of write lines each carrying a current for writing to at least one of the plurality of magnetic memory cells. Preferably, the plurality of magnetic write lines have soft magnetic properties and are preferably magnetic bit lines. For magnetic tunneling junction stacks within the magnetic memory cells, the magnetic bit lines are preferably significantly thicker than and closely spaced to the free layers of the magnetic memory cells.

Abstract: A method and system for reading a magnetic memory including a plurality of magnetic elements is disclosed. The method and system include determining a first resistance of at least one of the plurality of magnetic elements. The method and system also include applying a disturb magnetic field to the magnetic element(s) and determining a second resistance of the magnetic element(s) while the disturb magnetic field is applied. The method and system further include comparing the first resistance to the second resistance. Consequently, the state(s) of the magnetic element(s) can be determined without the use of a separate reference element.

Abstract: A magnetic random access memory (MRAM) array and method for making the MRAM array are disclosed. The MRAM array includes magnetic storage cells, global word lines, magnetic word lines, read bit lines, selection devices, and write bit lines. Each magnetic word line has segments. Each segment is coupled with the global word line(s) such that each segment is separately selectable. Each segment is also coupled to a portion of the magnetic storage cells. The read bit lines are oriented at an angle with respect to the magnetic word lines. The read bit lines are coupled with the magnetic cells through the selection devices. The write bit lines are substantially parallel to the read bit lines. Preferably, the magnetic word lines include soft magnetic materials and are coupled to each magnetic storage cell through a thin, nonmagnetic layer. To reduce interference from currents in global word lines, the global word lines are also substantially parallel to the magnetic word lines.

Abstract: A method and system for providing a magnetic memory is disclosed. The magnetic memory includes a magnetic element. The magnetic element is written using a first write line and a second write line and resides at an intersection between the first and second write lines. The second write line is oriented at an angle to the first write line. The second write line has a top and at least one side. At least a portion of the second write line is covered by an insulating layer. A magnetic layer covers a portion of the insulating layer. The portion of the insulating layer resides between the magnetic layer and the second write line. The magnetic layer includes a soft magnetic material.