Abstract: In a semiconductor device, a thin film resistor is formed by making use of an interconnect structure and etching back the layers over the glue layer of the interconnect structure and using the glue layer as a thin film resistor.

Abstract: An LDMOS structure which provides for reduced hot carrier effects. The reduction in hot carrier effects is achieved by increasing the size of the drain region of the LDMOS relative to the size of the source region. The larger size of the drain region reduces the concentration of electrons entering the drain region. This reduction in the concentration of electrons reduces the number of impact ionizations, which in turn reduces the hot carrier effects. The overall performance of the LDMOS is improved by reducing the hot carrier effects.

Abstract: A method for making an electrically programmable and erasable memory cell is disclosed. Specifically, a method for creating a floating gate using shallow trench isolation-type techniques is utilized to provide a floating gate having sharply defined tip characteristics. A first insulating layer is formed over a substrate. A conductive material is formed over the first insulating layer. A trench is defined in the conductive layer. This trench is filled with an oxide which is used as a mask to define tips of the floating gate during an etching process which defines the edges of the floating gate. After the floating gate has been etched, a tunneling oxide deposited over the floating gate. A conductive material is then formed over the tunneling oxide.

Abstract: In a ESD protection clamp, breakdown and triggering voltage of the structure are reduced by introducing an internal zener diode structure that has a lower avalanche breakdown than the p-n junction of the ESD device. This introduces extra holes into the source junction region causing electrons to be injected into the junction and into the drain junction region to increase the carrier multiplication rate to increase the current density and lower the triggering voltage and breakdown voltage of devices such as NMOS devices or LVTSCRs.

Abstract: A method for manufacturing a non-volatile memory device, the device having a core memory cell region and a periphery region, comprising the steps of: forming memory cell gate structures in the core memory cell region; forming active regions adjacent to the gate structure through a blanket implant; forming an implant/etch mask; implanting an impurity into one of the active regions; etching an oxide layer in the implant region; and forming active devices in the periphery region. In a further aspect, the method comprises method of performing a self aligned source etch in forming a memory device, comprising: forming resist spacers adjacent to the channel regions of the memory device; and etching the oxide layer.

Abstract: A color active pixel sensor cell is formed by utilizing four photodiodes which are each covered with a layer of oxide. The thicknesses of the layers of oxide are set so that a first layer of oxide prohibits red light from entering the first photodiode, a second layer of oxide prohibits green light from entering the second photodiode, a third layer of oxide prohibits blue light from entering the third photodiode, and a fourth layer of oxide allows visible light to enter the fourth photodiode. The amount of red light received by the cell is then determined by subtracting the light energy collected by the first photodiode from the light energy collected by the fourth photodiode. Similarly, the amount of green and blue light received by the cell is determined by subtracting the light energy collected by the second and third photodiodes, respectively, from the amount of light energy collected by the fourth photodiode.