Abstract: An electrochemical device (such as a battery) includes at least one electrode having a fluid surface, which may employ a surface energy effect to maintain a position of the fluid surface and/or to modulate flow within the fluid. Fluid-directing structures may also modulate flow or retain fluid in a predetermined pattern. An electrolyte within the device may also include an ion-transport fluid, for example infiltrated into a porous solid support.

Abstract: Lidded chip packages are provided in which an optoelectronic device chip has microelectronic circuits exposed at a surface of the chip with a lid mounted to overlie the optoelectronic device and the microelectronic circuits. An opaque film may be attached to the lid to overlie the microelectronic circuits while exposing the optoelectronic device. Lidded chip packages are also provided in which the lid overlies an active or passive device mounted to the chip. Wiring traces may be embedded within an adhesive between the lid and the chip.

Abstract: A method of making a plurality of sealed assemblies is provided which includes a) assembling a first element to a second element so that a bottom surface of the first element faces downwardly toward a front surface of the second element and a top surface of the first element faces upwardly away from the second element; and (b) forming ring seals surrounding regions of the front surface of the second element by introducing flowable material between the first element and the second element from the top surface of the first element through openings in the first element. A chip is provided which includes: (a) a body defining a front surface and one or more circuit elements on or within the body; (b) one or more bond pads exposed at the front surface in a bond pad region; and (c) a metallic ring exposed at the front surface, the ring substantially surrounding the bond pad region. Sealed chip assemblies are formed by sealing an array of the chips, e.g., in wafer form, to a cap element.

Abstract: Methods are provided for fabricating packaged chips having protective layers, e.g., lids or other overlying layers having transparent, partially transparent, or opaque characteristics or a combination of such characteristics. Methods are provided for fabricating the packaged chips. Lidded chip structures and assemblies including lidded chips are also provided.

Abstract: Methods are provided for fabricating packaged chips, each packaged chip having a protective layer, e.g., a transparent lid, metallic enclosure layer, shield layer, etc., and methods are provided for manufacturing such protective layer to be incorporated into a packaged chip. Lidded chip structures, and assemblies are also provided which include lidded chips.

Abstract: Methods for making a microelectronic component including a plurality of conductive posts extending and projecting away from a flexible substrate, wherein at least some of the conductive posts are electrically connected to a plurality of traces exposed on the flexible substrate.

Abstract: Provided are connection structures for a microelectronic device and methods for forming the structure. A substrate is included having opposing surfaces and a plurality of holes extending through the surfaces. Also included is a plurality of electrically conductive posts. Each post extends from a base to a tip located within a corresponding hole of the substrate. An additional substrate may be provided such that the base of each post is located on a surface thereof. Additional electrically conductive posts may be provided having tips in corresponding holes of the additional substrate. Optionally, a dielectric material may be placed between the substrate and the posts.

Abstract: A packaged microelectronic device is provided which includes: (a) a unit having a chip with an upwardly-facing front surface and a downwardly-facing rear surface, a lid overlying at least a portion of the front surface of the chip, the lid having a top surface facing upwardly away from the chip and unit connections exposed at the top surface of the lid. At least some of the unit connections are electrically connected to the chip. The packaged microelectronic device also includes a package structure including structure defining package terminals, at least some of the package terminals being electrically connected to the chip. The package structure, the unit or both define a downwardly-facing bottom surface of the package, the terminals being exposed at the bottom surface.

Abstract: Capped chips and methods of forming a capped chip are provided in which electrical interconnects are made by conductive elements which extend from bond pads of a chip at least partially through a plurality of through holes of a cap. The electrical interconnects may be solid, so as to form seals extending across the through holes. In some cases, stud bumps extend from the bond pads, forming parts of the electrical interconnects. In some cases, a fusible conductive medium forms a part of the electrical interconnects.

Abstract: A microelectronic package is provided that includes a microelectronic device and a cover. The device and the cover are typically substantially immobilized relative to each other. The cover typically has a higher coefficient of thermal expansion while the device has a higher effective stiffness. The package may be formed in wafer-level processes.

Abstract: Image sensors are provided having a plurality of photodetectors in a detector layer Optionally, an optically transparent substrate is provided for a rear-illuminated sensor architecture. The photodetectors may be arranged in three or more arrays. Typically, each array is contiguous and is associated with light of a different color and/or wavelength. In addition, the arrays may be coplanar, or, in the alternative, located at increasing distances from a light-receiving surface in an at least partially nonoverlapping manner. Also provided are image sensor packages.

Abstract: A microelectronic device includes a chip having a front surface and a rear surface, the front surface having an active region and a plurality of contacts exposed at the front surface outside of the active region. The device further includes a lid overlying the front surface. The lid has edges bounding the lid, at least one of the edges including one or more outer portions and one or more recesses extending laterally inwardly from the outer portions, with the contacts being aligned with the recesses and exposed through them.

Abstract: An electronic camera module incorporates a sensor unit (20) having a semiconductor chip (22) such as a CCD imager and a cover (34) overlying the front surface of the chip. An optical unit (50) includes one or more optical elements such as lenses (58). The optical unit has engagement features (64) which abut alignment features on the sensor unit as, for example, portions (44) of the cover outer surface (38), so as to maintain a precise relationship between the optical unit and sensor unit.

Abstract: Provided are connection structures for a microelectronic device and methods for forming the structure. A substrate is included having opposing surfaces and a plurality of holes extending through the surfaces. Also included is a plurality of electrically conductive posts. Each post extends from a base to a tip located within a corresponding hole of the substrate. An additional substrate may be provided such that the base of each post is located on a surface thereof. Additional electrically conductive posts may be provided having tips in corresponding holes of the additional substrate. Optionally, a dielectric material may be placed between the substrate and the posts.

Abstract: As disclosed herein, structures and methods are provided for forming capped chips. As provided by the disclosed method, a metal base pattern is formed on a chip insulated from wiring of the chip, and a cap is formed including a metal. The cap is joined to the metal base pattern on the chip to form the capped chip. In one embodiment, a front surface of the chip is exposed which extends from a contact of the chip to an edge of the chip. In another embodiment, a conductive connection is formed to the contact, the conductive connection extending from the contact to a terminal at an exposed plane above the front surface of the chip.

Abstract: A microelectronic package includes a microelectronic element having faces and contacts, and a flexible substrate spaced from and overlying a first face of the microelectronic element, the flexible substrate having conductive pads facing away from the first face of the microelectronic element. The package includes a plurality of spheres attached to the conductive pads of the flexible substrate and projecting away from the first face of the microelectronic element, each sphere having a contact surface remote from the conductive pads, the contact surfaces of the spheres including a contact metal devoid of solder. The package also includes a plurality of support elements disposed between the microelectronic element and the substrate for supporting the flexible substrate over the microelectronic element, the spheres being offset from the support elements.

Abstract: An array of chips spaced apart from one another by chip spacing distances, as, for example, an array of chips on a wafer dicing tape is juxtaposed with an array of chip receiving elements spaced apart from one another by receiving element spacing distances different from the chip spacing distances, as, for example, an array of substrates or fixtures spaced apart from one another at distances substantially larger than the chip spacing distances. The juxtaposing step is performed so that a set of chips including less than all of the chips in the array of chips is aligned with a set of the chip receiving elements. This set of chips is transferred to the set of chip receiving elements while the arrays are aligned with one another. The cycle may be repeated using the same or different array of chips, and using the same or different array of chip receiving elements.

Abstract: A solid-state image sensor including a package with an element for both covering and protecting the sensor device and also filtering portions, e.g., infrared portions, of the incident light beam. The image sensor module includes a package to receive the image sensor integrated circuit chip, with the image sensor integrated circuit chip being bonded to the package, and an infrared filter overlaying the image sensor integrated circuit chip and likewise bonded to the package. This provides both a hermetic seal for the image sensor integrated circuit chip and filters or attenuates the incident infrared light.

Abstract: A microelectronic package is provided in which a first chip having active elements, e.g. amplifying elements, and passive elements, e.g. resistors, capacitors and inductors, is mounted in electrical communication with a microelectronic element having conductive patterns opposing a front face of the first chip. Absorptive material patterns are disposed between the conductive patterns of the microelectronic element and at least some of the passive elements while leaving at least some of the active elements exposed so as to attenuate radio frequency energy propagated by wave between the passive devices and conductive patterns of the microelectronic element. A packaged chip is also provided in which a chip is disposed beneath a package element, the chip having an opening which extends between a front face and a rear face of the chip, a conductor being disposed in the opening which is conductively connected to a conductive element of the package element.

Abstract: Various embodiments of packaged chips and ways of fabricating them are disclosed herein. One such packaged chip disclosed herein includes a chip having a front face, a rear face opposite the front face, and a device at one of the front and rear faces, the device being operable as a transducer of at least one of acoustic energy and electromagnetic energy, and the chip including a plurality of bond pads exposed at one of the front and rear faces. The packaged chip includes a package element having a dielectric element and a metal layer disposed on the dielectric element, the package element having an inner surface facing the chip and an outer surface facing away from the chip. The metal layer includes a plurality of contacts exposed at at least one of the inner and outer surfaces, the contacts conductively connected to the bond pads.