Patents by Inventor David V. Horak

David V. Horak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8390079
    Abstract: A semiconductor chip including a substrate; a dielectric layer over the substrate; a gate within the dielectric layer, the gate including a sidewall; a contact contacting a portion of the gate and a portion of the sidewall; and a sealed air gap between the sidewall, the dielectric layer and the contact.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: March 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: David V. Horak, Elbert E. Huang, Charles W. Koburger, III, Douglas C. La Tulipe, Jr., Shom Ponoth
  • Patent number: 8383490
    Abstract: After formation of a semiconductor device on a semiconductor-on-insulator (SOI) layer, a first dielectric layer is formed over a recessed top surface of a shallow trench isolation structure. A second dielectric layer that can be etched selective to the first dielectric layer is deposited over the first dielectric layer. A contact via hole for a device component located in or on a top semiconductor layer is formed by an etch. During the etch, the second dielectric layer is removed selective to the first dielectric layer, thereby limiting overetch into the first dielectric layer. Due to the etch selectivity, a sufficient amount of the first dielectric layer is present between the bottom of the contact via hole and a bottom semiconductor layer, thus providing electrical isolation for the ETSOI device from the bottom semiconductor layer.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: February 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Su Chen Fan, Balasubramanian S. Haran, David V. Horak
  • Publication number: 20130043556
    Abstract: A size-filtered metal interconnect structure allows formation of metal structures having different compositions. Trenches having different widths are formed in a dielectric material layer. A blocking material layer is conformally deposited to completely fill trenches having a width less than a threshold width. An isotropic etch is performed to remove the blocking material layer in wide trenches, i.e., trenches having a width greater than the threshold width, while narrow trenches, i.e., trenches having a width less than the threshold width, remain plugged with remaining portions of the blocking material layer. The wide trenches are filled and planarized with a first metal to form first metal structures having a width greater than the critical width. The remaining portions of the blocking material layer are removed to form cavities, which are filled with a second metal to form second metal structures having a width less than the critical width.
    Type: Application
    Filed: August 17, 2011
    Publication date: February 21, 2013
    Applicant: International Business Machines Corporation
    Inventors: David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
  • Patent number: 8368146
    Abstract: A finFET structure and method of manufacture such structure is provided with lowered Ceff and enhanced stress. The finFET structure includes a plurality of finFET structures and a stress material forming part of a gate stack and in a space between adjacent ones of the plurality of finFET structures.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: February 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, David V. Horak, Hemanth Jagannathan, Charles W. Koburger, III
  • Publication number: 20130026570
    Abstract: After formation of a semiconductor device on a semiconductor-on-insulator (SOI) layer, a first dielectric layer is formed over a recessed top surface of a shallow trench isolation structure. A second dielectric layer that can be etched selective to the first dielectric layer is deposited over the first dielectric layer. A contact via hole for a device component located in or on a top semiconductor layer is formed by an etch. During the etch, the second dielectric layer is removed selective to the first dielectric layer, thereby limiting overetch into the first dielectric layer. Due to the etch selectivity, a sufficient amount of the first dielectric layer is present between the bottom of the contact via hole and a bottom semiconductor layer, thus providing electrical isolation for the ETSOI device from the bottom semiconductor layer.
    Type: Application
    Filed: July 27, 2011
    Publication date: January 31, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Su Chen Fan, Balasubramanian S. Haran, David V. Horak
  • Publication number: 20130026635
    Abstract: A hybrid interconnect structure containing copper regions that have different impurities levels within a same opening is provided. In one embodiment, the interconnect structure includes a patterned dielectric material having at least one opening located therein. A dual material liner is located at least on sidewalls of the patterned dielectric material within the at least one opening. The structure further includes a first copper region having a first impurity level located within a bottom region of the at least one opening and a second copper region having a second impurity level located within a top region of the at least one opening and atop the first copper region. In accordance with the present disclosure, the first impurity level of the first copper region is different from the second impurity level of the second copper region.
    Type: Application
    Filed: July 27, 2011
    Publication date: January 31, 2013
    Applicant: International Business Machines Corporation
    Inventors: Chih-Chao Yang, David V. Horak, Charles W. Koburger, III, Shom Ponoth
  • Publication number: 20130023115
    Abstract: A method includes depositing a dummy fill material over exposed portions of a substrate and a gate stack disposed on the substrate, removing portions of the dummy fill material to expose portions of the substrate, forming a layer of spacer material over the exposed portions of the substrate, the dummy fill material and the gate stack, removing portions of the layer of spacer material to expose portions of the substrate and the dummy fill material, depositing a dielectric layer over the exposed portions of the spacer material, the substrate, and the gate stack, removing portions of the dielectric layer to expose portions of the spacer material, removing exposed portions of the spacer material to expose portions of the substrate and define at least one cavity in the dielectric layer, and depositing a conductive material in the at least one cavity.
    Type: Application
    Filed: September 6, 2012
    Publication date: January 24, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Su Chen Fan, David V. Horak, Sivananda K. Kanakasabapathy
  • Patent number: 8354751
    Abstract: An interconnect structure having enhanced electromigration resistance is provided in which a lower portion of a via opening includes a multi-layered liner. The multi-layered liner includes, from a patterned surface of a dielectric material outwards, a diffusion barrier, a multi-material layer and a metal-containing hard mask. The multi-material layer includes a first material layer comprised of residue from an underlying dielectric capping layer, and a second material layer comprised of residue from an underlying metallic capping layer. The present invention also provides a method of fabricating such an interconnect structure which includes the multi-layered liner within a lower portion of a via opening formed within a dielectric material.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: January 15, 2013
    Assignee: International Business Machines Corporation
    Inventors: David V. Horak, Shom Ponoth, Chih-Chao Yang
  • Publication number: 20130009282
    Abstract: A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure.
    Type: Application
    Filed: September 13, 2012
    Publication date: January 10, 2013
    Applicant: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, David V. Horak, Elbert E. Huang, Satyanarayana V. Nitta, Takeshi Nogami, Shom Ponoth, Terry A. Spooner
  • Publication number: 20130009249
    Abstract: A finFET structure and method of manufacture such structure is provided with lowered Ceff and enhanced stress. The finFET structure includes a plurality of finFET structures and a stress material forming part of a gate stack and in a space between adjacent ones of the plurality of finFET structures.
    Type: Application
    Filed: September 13, 2012
    Publication date: January 10, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. BASKER, David V. Horak, Hemanth JAGANNATHAN, Charles W. KOBURGER, III
  • Publication number: 20130012017
    Abstract: A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure.
    Type: Application
    Filed: September 13, 2012
    Publication date: January 10, 2013
    Applicant: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, David V. Horak, Elbert E. Huang, Satyanarayana V. Nitta, Takeshi Nogami, Shom Ponoth, Terry A. Spooner
  • Patent number: 8349674
    Abstract: Embodiments of the present invention provide a method of forming a semiconductor structure. The method includes creating an opening inside a dielectric layer, the dielectric layer being formed on top of a substrate and the opening exposing a channel region of a transistor in the substrate; depositing a work-function layer lining the opening and covering the channel region; forming a gate conductor covering a first portion of the work-function layer, the first portion of the work-function layer being on top of the channel region; and removing a second portion of the work-function layer, the second portion of the work-function layer surrounding the first portion of the work-function layer, wherein the removal of the second portion of the work-function layer insulates the first portion of the work-function layer from rest of the work-function layer.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: January 8, 2013
    Assignee: International Business Machines Corporation
    Inventors: Shom Ponoth, David V. Horak, Charles W. Koburger, III, Chih-Chao Yang
  • Publication number: 20120329275
    Abstract: A metal layer is deposited on a planar surface on which top surfaces of underlying metal vias are exposed. The metal layer is patterned to form at least one metal block, which has a horizontal cross-sectional area of a metal line to be formed and at least one overlying metal via to be formed. Each upper portion of underlying metal vias is recessed outside of the area of a metal block located directly above. The upper portion of the at least one metal block is lithographically patterned to form an integrated line and via structure including a metal line having a substantially constant width and at least one overlying metal via having the same substantially constant width and borderlessly aligned to the metal line. An overlying-level dielectric material layer is deposited and planarized so that top surface(s) of the at least one overlying metal via is/are exposed.
    Type: Application
    Filed: September 8, 2012
    Publication date: December 27, 2012
    Applicant: International Business Machines Corporation
    Inventors: Shom Ponoth, David V. Horak, Charles W. Koburger, III, Chih-Chao Yang
  • Publication number: 20120326237
    Abstract: Embodiments of the present invention provide a structure. The structure includes a plurality of field-effect-transistors having gate stacks formed on top of a semiconductor substrate, the gate stacks having spacers formed at sidewalls thereof; and one or more conductive contacts formed directly on top of the semiconductor substrate and interconnecting at least one source/drain of one of the plurality of field-effect-transistors to at least one source/drain of another one of the plurality of field-effect-transistors, wherein the one or more conductive contacts is part of a low-profile local interconnect that has a height lower than a height of the gate stacks.
    Type: Application
    Filed: June 27, 2011
    Publication date: December 27, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shom Ponoth, David V. Horak, Charles W. Koburger, III, Chih-Chao Yang
  • Publication number: 20120329267
    Abstract: A method of forming a semiconductor structure includes forming a sacrificial conductive material layer. The method also includes forming a trench in the sacrificial conductive material layer. The method further includes forming a conductive feature in the trench. The method additionally includes removing the sacrificial conductive material layer selective to the conductive feature. The method also includes forming an insulating layer around the conductive feature to embed the conductive feature in the insulating layer.
    Type: Application
    Filed: June 21, 2011
    Publication date: December 27, 2012
    Applicant: International Business Machines Corporation
    Inventors: David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
  • Publication number: 20120282779
    Abstract: A cap material layer is deposited on a metal nitride layer. An antireflective coating (ARC) layer, an organic planarizing layer (OPL), and patterned line structures are formed upon the cap material layer. The pattern in the patterned line structures is transferred into the ARC layer and the OPL. Exposed portions of the cap material layer are etched simultaneously with the etch removal of the patterned line structures and the ARC layer. The OPL is employed to etch the metal nitride layer. The patterned cap material layer located over the metal nitride layer protects the top surface of the metal nitride layer, and enables high fidelity reproduction of the pattern in the metal nitride layer without pattern distortion. The metal nitride layer is subsequently employed as an etch mask for pattern transfer into an underlying layer.
    Type: Application
    Filed: May 6, 2011
    Publication date: November 8, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John C. Arnold, Sean D. Burns, Matthew E. Colburn, David V. Horak, Yunpeng Yin
  • Publication number: 20120273848
    Abstract: Each gate structure formed on the substrate includes a gate dielectric, a gate conductor, a first etch stop layer, and a gate cap dielectric. A second etch stop layer is formed over the gate structures, gate spacers, and source and drain regions. A first contact-level dielectric layer and a second contact-level dielectric layer are formed over the second etch stop layer. Gate contact via holes extending at least to the top surface of the gate cap dielectrics are formed. Source/drain contact via holes extending to the interface between the first and second contact-level dielectric layers are subsequently formed. The various contact via holes are vertically extended by simultaneously etching exposed gate cap dielectrics and exposed portions of the first contact-level dielectric layer, then by simultaneously etching the first and second etch stop layers. Source/drain contact vias self-aligned to the outer surfaces gate spacers are thereby formed.
    Type: Application
    Filed: April 28, 2011
    Publication date: November 1, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Su C. Fan, David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
  • Patent number: 8299625
    Abstract: A metal layer is deposited on a planar surface on which top surfaces of underlying metal vias are exposed. The metal layer is patterned to form at least one metal block, which has a horizontal cross-sectional area of a metal line to be formed and at least one overlying metal via to be formed. Each upper portion of underlying metal vias is recessed outside of the area of a metal block located directly above. The upper portion of the at least one metal block is lithographically patterned to form an integrated line and via structure including a metal line having a substantially constant width and at least one overlying metal via having the same substantially constant width and borderlessly aligned to the metal line. An overlying-level dielectric material layer is deposited and planarized so that top surface(s) of the at least one overlying metal via is/are exposed.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: Shom Ponoth, David V. Horak, Charles W. Koburger, III, Chih-Chao Yang
  • Patent number: 8298954
    Abstract: A cap material layer is deposited on a metal nitride layer. An antireflective coating (ARC) layer, an organic planarizing layer (OPL), and patterned line structures are formed upon the cap material layer. The pattern in the patterned line structures is transferred into the ARC layer and the OPL. Exposed portions of the cap material layer are etched simultaneously with the etch removal of the patterned line structures and the ARC layer. The OPL is employed to etch the metal nitride layer. The patterned cap material layer located over the metal nitride layer protects the top surface of the metal nitride layer, and enables high fidelity reproduction of the pattern in the metal nitride layer without pattern distortion. The metal nitride layer is subsequently employed as an etch mask for pattern transfer into an underlying layer.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: John C. Arnold, Sean D. Burns, Matthew E. Colburn, David V. Horak, Yunpeng Yin
  • Patent number: 8288268
    Abstract: A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure.
    Type: Grant
    Filed: April 29, 2010
    Date of Patent: October 16, 2012
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, David V. Horak, Elbert E. Huang, Satyanarayana V. Nitta, Takeshi Nogami, Shom Ponoth, Terry A. Spooner