Abstract: A system and method for delaying packet transmissions within source devices and network bridges for the purpose of reducing the worst-case delays associated with forwarding of time-sensitive packets through a bridged network. The minimal bridged network system include a first device node attached to a first network link, a second device node attached to a second network link, and a bridge connecting the first network link to the second network link. The method and system includes shaping the traffic within a source device or bridge (shaping involves spreading bunched packets over time). Within a bridge, shaping occurs at each output port of the bridge, applying a distinct shaper to the traffic coming from each of the input ports, as well as distinct shapers for the distinct traffic class coming each of the input ports.

Abstract: A method and apparatus for configuring signal lines with idle codes is disclosed. According to one embodiment, data transmission system (100) may include encoders (112, 114, 116 and 118) that transmit data over signal line lanes (Lane 0 to Lane n). In an idle state, an encoder (112, 114, 116 and 118) may output one of at least two idle codes (IDLE A and IDLE B). One idle code (IDLE A) may indicate a first lane of a group of lanes. Another idle code (IDLE B) may indicate subsequent lanes of a group of lanes.

Abstract: A search engine system (100) is disclosed that can include at least one content addressable memory (CAM) device (102) arranged in a cascade configuration with at least one memory device (104), such as a static random access memory (SRAM). A CAM device (102) and memory device (104) may be connected to one another by point-to-point unidirectional connections. Command data issued by a device, such as a network processing unit (NPU) (110), can flow through all devices beginning with a CAM device (102) and eventually to a memory device (104). A memory device (104) can compare its own current result data with that of a previous device in a flow (such as another RAM device), and generate an output response.

Abstract: According to one embodiment, a content addressable memory (CAM) device (100) may include a number of segments (102 or 104). Search target compare circuits (110 and 112) can compare a target value TARGET to programmable information values (PIV0 and PIV1) associated with a particular segment (102 and 104). If a search target value TARGET matches a programmable information value (PIV0 and PIV1), search operations may be performed in a segment (102 or 104). If a search target value TARGET does not match a programmable information value, (PIV0 and PIV1), search operations may be prevented within a segment (102 or 104).

Abstract: A search engine system (100) is disclosed that can include at least one content addressable memory (CAM) device (102) arranged in a cascade configuration with at least one memory device (104), such as a static random access memory (SRAM). A CAM device (102) and memory device (104) may be connected to one another by point-to-point unidirectional connections. Command data issued by a device, such as a network processing unit (NPU) (110), can flow through all devices beginning with a CAM device (102) and eventually to a memory device (104). A memory device (104) can compare its own current result data with that of a previous device in a flow (such as another RAM device), and generate an output response.

Abstract: An asynchronous control mechanism packet is used to send control messages and information to one or more bridge devices within a network of buses of devices. The asynchronous control mechanism packet is addressed to a device on one of the buses and is intercepted by one or more appropriate bridge devices along the path to the destination device. The asynchronous control mechanism packet is targeted at a particular bridge device or used to send control messages and information to bridge devices along a particular communications route between two devices. The asynchronous control mechanism packet includes a designation specifying that it is an asynchronous control mechanism packet and should be treated accordingly. This designation is recognized by the appropriate bridge devices. Preferably, this designation is included within the extended transaction code field of the packet. In an alternate embodiment, the designation is included within a transaction code field of the packet.

Abstract: A method and apparatus for configuring signal lines with idle codes is disclosed. According to one embodiment, data transmission system (100) may include encoders (112, 114, 116 and 118) that transmit data over signal line lanes (Lane 0 to Lane n). In an idle state, an encoder (112, 114, 116 and 118) may output one of at least two idle codes (IDLE A and IDLE B). One idle code (IDLE A) may indicate a first lane of a group of lanes. Another idle code (IDLE B) may indicate subsequent lanes of a group of lanes.

Abstract: According to a data packet framing method of one embodiment, a data packet (100) may include a combination control character (102) that may convey framing information FLAG (102-0) and a code information CODE (102-1). Framing information FLAG (102-0) can indicate a start of a packet, and a code information CODE (102-1) can indicate another feature of a packet, such as size. A combination control character (102) may preferably be no larger than a data character of a data packet.

Abstract: According to one embodiment, a content addressable memory (CAM) device (100) may include a number of CAM entry sets (102-0 and 102-1), each of which includes multiple CAM entries. CAM (100) may also include multiple programmable information registers (PIRs) (104-0 and 104-1), each of which can be associated with a CAM entry set (102-0 and 102-1). PIRs (104-0 and 104-1) may be accessed in response to CAM commands. Values stores in PIRs (104-0 and 104-1) may control access to associated CAM entry sets (102-0 and 102-1) and/or be output in response to predetermined operations in an associated CAM entry set (102-0 and 102-1).

Abstract: A search engine system (100) and CAM device (300) are disclosed. A search engine system (100) may generate response packets (112) in response to requests packets (110) and include at least one content addressable memory (CAM) device (102-0) having an input interface (116-0) for receiving data packets and an output interface (116-1) for transmitting data packets.

Abstract: According to an embodiment, a content addressable memory (CAM) device (104) may be capable of executing a “restricted” search operation. A restricted search operation (an “explore” or “search beyond” operation) may compare only a portion of the CAM entries to a search key device. Preferably, a restricted search operation may restrict searches to entries having an index value greater than a received search index value.

Abstract: A method and system thereof for organizing and accessing stored data in a mass storage unit such as a hard disk device. An object is associated with the stored data, and a unique object identifier is derived for and assigned to the object by the hard disk device. The object is addressed by its object identifier. The object is maintained in a hierarchical organization with other objects. The hierarchical organization includes an object list that contains the object identifier and also includes object identifiers for the other objects. Commands are defined for accessing and operating on the stored data using the object identifier for the object associated with the data. Thus, objects are named and organized on a hard disk device in an audio/visual network in a uniform manner, and the objects are represented to devices in the AV network so that they can be readily accessed and retrieved by those devices.

Abstract: A method for assigning chip identification (ID) values is disclosed. Unique chip ID values may be assigned to chips (106-0 to 106-5) in a system (100) having multiple branches (112-0 and 112-1). After chip IDs have been assigned to chips of a first branch (112-0) a command processing system (104) may issue an end of branch indication. Chip IDs may then be assigned to chips of a next branch (112-1).

Abstract: Within the routing method and apparatus of the present invention, a router is coupled to multiple buses, each of the buses having one or more nodes. A node on a first bus structure sending a communication to a node on a second bus structure includes an address value within the communication addressed into the address space of the router. When the packet is received, the router then preferably uses a routing value within the address value to determine the bus number and node number of the target node. The router then uses this bus number and node number to remap the address value to the target node. This remapped address value is then included within the packet and transmitted on the appropriate bus structure directed to the appropriate node. In an alternate embodiment, the address value in a packet received by the router includes a table index value and a direct offset value.

Abstract: According to one embodiment, a search engine device (100) may include an input (102), search portion (106), and a vote portion (108). A vote portion (108) may receive responses to a search request at inputs. According to precedence information in received responses, a vote portion (108) may generate an output response having its own precedence information.

Abstract: A system and method for efficiently performing scheduling operations in an electronic device comprises an allocation manager that initially evaluates a task scheduling request based upon certain request parameters. The request parameters may include a resource requirement and an execution interval. If the task scheduling request is granted, then the allocation manager adds the corresponding task to a prioritized task table. A scheduling manager may then reference the task table to efficiently identify the next task for scheduling and execution on the electronic device.

Abstract: A method of maintaining communications in a bus bridge interconnect including a plurality of buses linked by at least one bus bridge. The method includes receiving a change indication signal from a talker node, performing an address resolution protocol in response to the change indication signal to find an updated node identification address(“nodeID”) for a listener node using a extended unique identifier (“EUI”) of the listener node, and storing the updated listener nodeID with the listener node EUI.

Abstract: A content addressable memory (CAM) device (100) may include a CAM array (102), a CAM array access circuit (104), and a preclassifier circuit (106). A preclassifier circuit (106) may selectively modify portions of an input data value before such an input data value is applied to a CAM array (102). In particular embodiments, a preclassifier circuit (106) may compare a compare portion of an input data value to one or more ranges. If such a portion falls within a range, a preclassifier may substitute a compare portion with a range code value to form a modified input data value.

Abstract: A decoder circuit (100) is disclosed that may include “string” decoders (102-0 and 102-1), a compare circuit (104) and an enable circuit (106). String decoders (102-0 and 102-1) may provide “one-hot” or “string” decoding. One-hot decoding may activate one pre-decode signal. String decoding may activate one or more pre-decode signals. A compare circuit (104) may receive at least two pre-decode signals from one string decoder (102-1) and compare such values to generate a comparison result CMP. An enable circuit may generate decoder output signals (DEC0-DEC(n?1)) according to a comparison result CMP.

Abstract: A first set of signals is transformed into a second set of signals having a more stable set of current requirements. The more stable current requirements of the second set of signals are achieved by encoding the second set of signals with either an equal number, nearly an equal number, a constant number, or nearly a constant number of logic ones and logic zeros. A communication channel is provided for carrying the second set of signals from the first node to a second node.