Abstract: The circuit of this invention includes a programmable circuit (PC) for storing an internal address and for producing logic levels (LL1, etc.) determined by that internal address and includes a first comparison circuit (CC1) and a second comparison circuit (CC2). The first comparison circuit (CC1) responds to the logic levels (LL1, etc.) representative of that internal address and to a first address signal (CA0, etc.) to generate a first match signal (CRFSN) determined by matching of the internal address and the first address signal (CA0, etc.). The second comparison circuit (CC2) responds to the logic levels (LL1) and to a second address signal (SF0, etc.) to generate a second match signal (SRSJN) determined by the matching of the internal address and the second address signal (SF0, etc.).

Abstract: A circuit is provided for replacing a defective signal path (94) of a plurality of like signal paths with a redundant signal path (95, 96). A redundant decoder (72) is programmable to respond to a plurality of predetermined addressing signals (RFn) that normally operate to address the defective signal path (94, ROWL1R and ROWL1L). The redundant decoder is operable to generate a disable signal (RREN) in response to the predetermined addressing signals (RFn) and also is operable to select a redundant signal path (95, 96) in response thereto. A decoding circuit (70, 74) normally decodes selected ones of a plurality of addressing signals (RFn) and selects at least one of a plurality of signal paths in response thereto. The decoding circuit (70, 74) is coupled to the redundant decoder (72) for receiving the disable signal (RREN) therefrom. In response to receiving this disable signal (RREN) the decoding circuit (70, 74) will not decode the preselected addressing signals (RFn).

Abstract: A circuit is provided for replacing a defective signal path (94) of a plurality of like signal paths with a redundant signal path (95, 96). A redundant decoder (72) is programmable to respond to a plurality of predetermined addressing signals (RFn) that normally operate to address the defective signal path (94, ROWL1R and ROWLIL). The redundant decoder is operable to generate a disable signal (RREN) in response to the predetermined addressing signals (RFn) and also is operable to select a redundant signal path (95, 96) in response thereto. A decoding circuit (70, 74) normally decodes selected ones of a plurality of addressing signals (RFn) and selects at least one of a plurality of signal paths in response thereto. The decoding circuit (70, 74) is coupled to the redundant decoder (72) for receiving the disable signal (RREN) therefrom. In response to receiving this disable signal (RREN) the decoding circuit (70, 74) will not decode the preselected addressing signals (RFn).

Abstract: A word or row line (38a, 38b) associated with at least one row of memory cells in an integrated circuit memory array (10) having a plurality of word lines is driven by a drive/boot generator signal (RLXH) by first generating this drive signal using a drive signal generator (20) that is formed in a peripheral area (14) of the chip (10). The drive signal (RLXH) is transmitted to each of a plurality of predecoders (40) that are formed within a memory cell array area (12) of the chip (10). At least one of the predecoders (40) is actuated to transmit the drive signal (RLXH) onto a selected one of a plurality of predecoder output lines (RDD0-RDD3) in response to predetermined addressing or row factor signals (RF0-RF19). The drive signal (RLXH) is transmitted on a selected predecoder output line (44) to each of a plurality of decoders (36) formed within the array area (12).

Abstract: A multiple frequency oscillator responds to a control signal to selectively produce an output signal having a first frequency or a second frequency. The oscillator includes a plurality of inverter stages (48.sub.1 -48.sub.5) with the input of each inverter stage coupled to the output of another inverter stage. At least one of the inverter stages includes first and second transistors (50,51) having current paths connected in parallel, a third transistor (52) having a current path connected in series with the current paths of the first and second transistors (50, 51) between a first voltage source (Vdd) and the inverter stage output, and a fourth transistor (53) having a current path connected between the inverter stage output and a second voltage source (Vss). The control electrodes of the first, third, and fourth transistors (50, 52, 53) are connected to the input of the inverter stage.

Abstract: During an active phase of operation of the circuit (70), a gate (38) of a transistor (14) is boosted to a first voltage level that is substantially above the voltage supply level (V.sub.dd). After the gate (38) is boosted, the signal node (12) is boosted by transmitting current through the current path of the transistor (14) from a first electrode (16) of a boosting capacitor (18). During a reset phase of operation of the circuit (70), a second electrode (26) of the capacitor (18) is discharged. This causes the withdrawl of the charge from the signal node (12) through the current path of the transistor (14) to the first electrode (16) of the boosting capacitor (18). A predetermined voltage level near the voltage supply level is established across the electrodes (16, 26) of the boosting capacitor (18) in response to this.

Abstract: An input circuit for an integrated circuit furnishes a level shifting buffer portion adjacent a respective bond pad carried at the margin of the substrate while furnishing a clocked or latched portion adjacent the internal circuit of the integrated circuit. A lead extending from the level shifting or buffer portion to the clocked or latched portion carries the external signal applied to the bond pad and level shifted by the level shifting or buffer portion. The lead is subject to the parasitic resistance and capacitance of the integrated circuit. A multiplexer can be used to select among the level shifting portions for applying a single signal to the clocked portion and the clocked or latched portion can be part of a larger latch that receives plural signals for transmission to the internal circuit at appropriate times.