Abstract: A test automation system for efficiently testing a wide range of devices, including embedded devices, IoT devices, mobile devices, and edge AI devices, is disclosed. The system employs a unique architecture and technical solutions to overcome limitations of existing testing platforms. It provides a comprehensive and flexible testing solution by incorporating modular components. The system includes a device integration package (DIP) that enables the system to communicate with and test any type of device. The system enables efficient management of diverse device types, streamlined test case creation and execution, and intelligent analysis of test results. Through its innovative design, the test automation system addresses the technical challenges associated with testing heterogeneous devices, enhancing the efficiency and effectiveness of the testing process.

Abstract: Method for SEL mitigation involves determining one or more base sets of signature vector components for each of a plurality of signal loading conditions experienced by a protected device in an operating state, each set of base signature vector components together comprising a base signature vector. The method further involves monitoring signature vector components for the protected device to determine a detected signature vector which is comprised of a set of detected signature vector components. The detected signature vector is compared to a dynamically selected base signature vector which is associated with the device state and signal loading condition which are currently active to differentiate between the occurrence of standard current surges associated with normal operation of the protected device and a non-standard current surge.

Abstract: Method for SEL mitigation involves determining one or more base sets of signature vector components for each of a plurality of signal loading conditions experienced by a protected device in an operating state, each set of base signature vector components together comprising a base signature vector. The method further involves monitoring signature vector components for the protected device to determine a detected signature vector which is comprised of a set of detected signature vector components. The detected signature vector is compared to a dynamically selected base signature vector which is associated with the device state and signal loading condition which are currently active to differentiate between the occurrence of standard current surges associated with normal operation of the protected device and a non-standard current surge.

Abstract: Method and system for Single Event Latchup (SEL) current surge mitigation involves monitoring data signals for a protected device and deriving from them a detected signature comprised of one or more detected signature vector components. The detected signature vector components are compared to previously stored signature vector components. Based on the comparing, the system selectively differentiates between the occurrence of standard power surges associated with normal operation of the protected device, and a non-standard current surge which requires cycling power of the protected device for continued proper functioning of the protected device.

Abstract: Method and system for Single Event Latchup (SEL) current surge mitigation involves monitoring data signals for a protected device and deriving from them a detected signature comprised of one or more detected signature vector components. The detected signature vector components are compared to previously stored signature vector components. Based on the comparing, the system selectively differentiates between the occurrence of standard power surges associated with normal operation of the protected device, and a non-standard current surge which requires cycling power of the protected device for continued proper functioning of the protected device.

Abstract: This invention generally relates to lighting controller, more particularly to electronic ballast circuits, sometimes referred to as electronic control gears (ECG) or gas discharge lamps. An electronic ballast for a gas discharge lamp, the electronic ballast comprising: a power input circuit to provide a dc voltage supply; a SEPIC converter having a converter input coupled to said dc voltage supply and having a dc voltage output; and a push-pull output stage coupled to said dc voltage output to provide an ac voltage for driving said lamp, said push-pull output stage comprising a pair of inductive elements each having a first connection to one another and to said dc voltage output and a second connection to a respective switch.

Abstract: The invention relates to swinging inductors of a stepped-gap construction. We describe an inductor core structure having first and second core segments, constructed and arranged such that distal ends of legs of the first core segment are paired with distal ends of legs of the second core segment in an opposing relation. The at least one distal ends of the first core segment has a ridge projecting therefrom and is paired with the at least one distal ends of the second core segment which has a ridge projecting therefrom in an opposing relation, such that opposingly paired projecting ridges form a cross arrangement.

Abstract: This invention generally relates to lighting controller, more particularly to electronic ballast circuits, sometimes referred to as electronic control gears (ECG) or gas discharge lamps. An electronic ballast for a gas discharge lamp, the electronic ballast comprising: a power input circuit to provide a dc voltage supply; a SEPIC converter having a converter input coupled to said dc voltage supply and having a dc voltage output; and a push-pull output stage coupled to said dc voltage output to provide an ac voltage for driving said lamp, said push-pull output stage comprising a pair of inductive elements each having a first connection to one another and to said dc voltage output and a second connection to a respective switch.

Abstract: The invention relates to swinging inductors of a stepped-gap construction. We describe an inductor core structure having first and second core segments, constructed and arranged such that distal ends of legs of the first core segment are paired with distal ends of legs of the second core segment in an opposing relation. The at least one distal ends of the first core segment has a ridge projecting therefrom and is paired with the at least one distal ends of the second core segment which has a ridge projecting therefrom in an opposing relation, such that opposingly paired projecting ridges form a cross arrangement.

Abstract: Method for predicting an average temperature of a conductive structural component (204) over an elongated length of the structural component. The method can include measuring (406) an electrical resistance of the structural component (204) between two locations (206, 208) spaced apart from each other. The method can also include predicting (408) an average temperature of the structural component (202) between the two locations based on the measuring step. Using the information gained in this step, a dimensional characteristic of the structural component (202) can be predicted (410) based on the average temperature.