Abstract: According to an aspect, a digital signal processor obtains a program instruction, selects a first real valued input or a second real valued input as a given real valued input (the first and second real valued inputs organized as adjacent elements of a first input vector), depending on an instruction type. The processor performs an arithmetic operation on the selected real valued input to provide a real valued result, and provides a first real valued output and a second real valued output during a first operation cycle (organized as adjacent elements of a second output vector). The real valued result is provided as the first real valued output and as the second real valued output, depending on the instruction type, and the second output vector is a real valued second output vector for real-complex multiplication with a complex valued third vector.

Abstract: An apparatus and method for creation of reordered vectors from sequential input data for block based decimation, filtering, interpolation and matrix transposition using a memory circuit for a Single Instruction, Multiple Data (SIMD) Digital Signal Processor (DSP). This memory circuit includes a two-dimensional storage array, a rotate-and-distribute unit, a read-controller and a write to controller, to map input vectors containing sequential data elements in columns of the two-dimensional array and extract reordered target vectors from this array. The data elements and memory configuration are received from the SIMD DSP.

Abstract: A class of digital signal processor instructions, comprising at least a first instruction type and a second instruction type, is proposed. The class of instructions may be added to the instruction set of a digital signal vector processor and a program instruction is selected from the digital signal processor instruction set. The digital signal processor is adapted to cause execution of a method comprising obtaining a program instruction, selecting a real valued input as one of a first real valued input and a second real valued input (the first and second real valued inputs organized as adjacent elements of a first input vector), performing an arithmetic operation on the selected real valued input to provide a real valued result, and providing a first real valued output and a second real valued output during a first operation cycle (the first and second real valued outputs organized as adjacent elements of a second output vector).

Abstract: An element selection unit (200) and a method therein for vector element selection. The element selection unit comprises a selector control circuit (404) and a selector data path circuit (406), which data path circuit comprises a plurality of layers of multiplexers. The element selection unit further comprises a receiving circuit (401) configured to receive an instruction to perform a selection of elements from an input vector. The selector control circuit (404) is configured to generate a multiplexer control signal for each multiplexer based on a bit map and on a plurality of relative offset values. The data path circuit is configured to propagate the elements comprised in the input vector through the plurality of layers of multiplexers towards an output vector based on the generated multiplexer control signals. The data path circuit is further configured to write the propagated elements to enabled elements of the output vector.

Abstract: An element selection unit (200) and a method therein for vector element selection. The element selection unit comprises a selector control circuit (404) and a selector data path circuit (406), which data path circuit comprises a plurality of layers of multiplexers. The element selection unit further comprises a receiving circuit (401) configured to receive an instruction to perform a selection of elements from an input vector. The selector control circuit (404) is configured to generate a multiplexer control signal for each multiplexer based on a bit map and on a plurality of relative offset values. The data path circuit is configured to propagate the elements comprised in the input vector through the plurality of layers of multiplexers towards an output vector based on the generated multiplexer control signals. The data path circuit is further configured to write the propagated elements to enabled elements of the output vector.

Abstract: An apparatus and method for creation of reordered vectors from sequential input data for block based decimation, filtering, interpolation and matrix transposition using a memory circuit for a Single Instruction, Multiple Data (SIMD) Digital Signal Processor (DSP). This memory circuit includes a two-dimensional storage array, a rotate-and-distribute unit, a read-controller and a write to controller, to map input vectors containing sequential data elements in columns of the two-dimensional array and extract reordered target vectors from this array. The data elements and memory configuration are received from the SIMD DSP.

Abstract: In a multi-radio device it is determined that a first radio application requests change to a first operational state during a time at which a second radio application is in or requests a second operational state. A local memory is accessed to determine a first and a second budget of resources for the respective first and second operational states of the respective first and second radio applications. There is at least one common resource among the first and second budgets. From resource allocation rules stored in the memory is determined that each of the common resources are mutually exclusive as between the first and second operational states of the respective first and second radio applications. As a result of the determining from the resource allocation rules, the request of the first radio application is granted by allocating resources according to the first budget for the first operational state while resources according to the second budget are allocated for the second operational state.