Abstract: A cutting device and method are provided for cutting a tire component. The cutting device comprises a support surface for supporting the tire component, a cutter which is movable along a cutting line for cutting through the tire component on the support surface, and a pressing device which is movable along the cutting line for pressing the tire component onto the support surface. The cutting device is arranged to move the pressing device from a first position at the support plane to a second position at a clearance height from said support plane in a clearance direction transverse or perpendicular to the support plane, and from the second position towards the first position in a pressing direction opposite to the clearance direction.

Abstract: According to one implementation of the present disclosure, a cache memory includes: a plurality of cache-lines, wherein each row of cache-lines comprises: tag bits of a tag-random access memory (tag-RAM); data bits of a data-random access memory (data-RAM), and a single set of retention bits corresponding to the tag-RAM. According to one implementation of the present disclosure, a method includes: sampling a single set of retention bits of a cache-line of a cache memory, where the cache-line comprises the single set of retention bits, tag-RAM and data-RAM, and where at least the single set of retention bits comprise eDRAM bitcells; and performing a refresh cycle of at least the data-RAM corresponding to the tag-RAM based on the sampled single set of retention bits.

Abstract: A system may include persistent storage containing representations of configuration items discovered in a managed network, where the configuration items include computing devices and software applications installed on the computing devices. One or more processors may be configured to: (i) obtain results of a vulnerability analysis performed on a software application, where the results indicate that the software application exhibits a vulnerability, (i) determine a count of computing devices on which the software application is installed, (iii) calculate a security threat score for the vulnerability, where the security threat score is based on a severity factor of the vulnerability and the count of computing devices, (iv) provide, to a first entity, a first indication of the software application and the vulnerability, and (v) provide, to a second entity, a second indication of the software application, the vulnerability, and the security threat score.

Abstract: An electro-optic display includes a backplane with at least one electrode, a layer of an electro-optic material disposed adjacent to the backplane, and a light-transmissive electrically-conductive layer disposed on the opposite side of the layer of electro-optic material from the backplane. The electro-optic display also includes a rod member disposed laterally adjacent to the backplane, the electro-optic material, and the light-transmissive electrically-conductive layer. A first barrier layer is disposed adjacent to the light-transmissive electrically-conductive layer and a first side of the rod member, and a second barrier is layer disposed on the backplane and a second side of the rod member. The second side is the opposite side of the rod member from the first side. A flexible barrier tape extends from an edge portion of the first barrier layer, around the rod member, to an edge portion of the second barrier layer.

Abstract: A system may include persistent storage containing representations of configuration items discovered in a managed network, where the configuration items include computing devices and software applications installed on the computing devices. One or more processors may be configured to: (i) obtain results of a vulnerability analysis performed on a software application, where the results indicate that the software application exhibits a vulnerability, (i) determine a count of computing devices on which the software application is installed, (iii) calculate a security threat score for the vulnerability, where the security threat score is based on a severity factor of the vulnerability and the count of computing devices, (iv) provide, to a first entity, a first indication of the software application and the vulnerability, and (v) provide, to a second entity, a second indication of the software application, the vulnerability, and the security threat score.

Abstract: Various implementations described herein relate to a device with a multi-transistor logic structure for use in memory architecture. In some applications, the multi-transistor logic structure may have a pair of P-type transistors that are arranged in a P-over-P multi-transistor stack. In other applications, the multi-transistor logic structure may have a pair of N-type transistors that are arranged in an N-over-N multi-transistor stack.

Abstract: Various implementations described herein relate to a method for manufacturing, or causing to be manufactured, multiple devices packaged within a single semiconductor die. The multiple devices may have first devices that are arranged in a first multi-transistor stack with a first P-N configuration. The multiple devices may have second devices that are arranged in a second multi-transistor stack with a second P-N configuration that is different than the first P-N configuration.

Abstract: Various implementations described herein are related to a device having multiple transistors in a single stack arranged as a cross-coupled bitcell latch. Also, the multiple transistors may be disposed in a multi-transistor stack configuration that is formed within a single monolithic semiconductor die. In some implementations, the multiple transistors may be arranged as a bitcell for single-port memory applications.

Abstract: In one implementation, a circuit includes: a comparator; a shift register chain coupled to the comparator; and one or more converters coupled to respective shift registers of the shift register chain, wherein the one or more converters are configured to convert a source of current from a first voltage to a second voltage, and wherein the circuit is configured to selectively transmit an output signal to the one or more converters. In one implementation, the circuit is configured to selectively control modulation for the one or more converters.

Abstract: According to one implementation of the present disclosure, a circuit structure is configured to store charge in a charge-based storage element, where the charge-based storage element is disposed at least partially in a shallow-trench-isolation (STI) region of the circuit. According to one implementation of the present disclosure, a method includes: providing a circuit structure disposed on a substrate and a shallow-trench-isolation (STI) region of a circuit; forming an opening of the substrate and the STI region by removing a portion of the substrate and STI region; placing a first liner material in the opening and on remaining portions of the substrate and the STI region; and depositing a first metal layer in the opening on the first liner material.

Abstract: According to one implementation of the present disclosure, a cache memory includes: a plurality of cache-lines, wherein each row of cache-lines comprises: tag bits of a tag-random access memory (tag-RAM); data bits of a data-random access memory (data-RAM), and a single set of retention bits corresponding to the tag-RAM. According to one implementation of the present disclosure, a method includes: sampling a single set of retention bits of a cache-line of a cache memory, where the cache-line comprises the single set of retention bits, tag-RAM and data-RAM, and where at least the single set of retention bits comprise eDRAM bitcells; and performing a refresh cycle of at least the data-RAM corresponding to the tag-RAM based on the sampled single set of retention bits.

Abstract: A ball game apparatus in which movements of a coded ball are detected by detector units and an automatic indication of a player’s score is given, where data relating to the ball are stored in a database connected to the detector units, the data including the code of a ball and a code relating to a player to whom the ball has been allocated, the ball being configured to temporarily store, and to intermittently transfer to the detector units and thence to the database, data relating to the ball’s movements. A rechargeable battery is contained within the ball, and is arranged to be charged by a battery charging system. Features of the game may be controlled by means of a player’s mobile telephone.

Abstract: Various implementations described herein are related to a device having a multi-device stack structure for use in multi-layered circuit architectures. The multi-device stack structure may have P-type transistors and N-type transistors that are arranged vertically in a multi-transistor stack configuration. In some implementations, the device may have a multi-device stack structure for use in multi-bit memory and/or logic architecture that is formed with complementary field effect transistor (CFET) technology.

Abstract: Provided are methods for isolating T-cells with T cell receptors (TCRs) optimized for reactivity to specific peptides and decreased cross-reactivity to non-target peptides. Advantageously, TCRs of the invention can be optimized to target cancer antigens and peptides while having reducing reactivity to healthy cells. Methods of the invention utilize a novel combination of culturing conditions that increase T-cell activation and allow for validation of TCR activity. Culturing conditions of the invention further reduce culturing times generally needed to achieve expanded reactive T-cells. Because of the robust nature of the activation and validation conditions of the present invention, variants of identified TCRs can also be optimized and validated for their response to peptides, including cancer peptides.

Abstract: Provided are methods for isolating T-cells with T cell receptors (TCRs) optimized for reactivity to specific peptides and decreased cross-reactivity to non-target peptides. Advantageously, TCRs of the invention can be optimized to target cancer antigens and peptides while having reducing reactivity to healthy cells. Methods of the invention utilize a novel combination of culturing conditions that increase T-cell activation and allow for validation of TCR activity. Culturing conditions of the invention further reduce culturing times generally needed to achieve expanded reactive T-cells. Because of the robust nature of the activation and validation conditions of the present invention, variants of identified TCRs can also be optimized and validated for their response to peptides, including cancer peptides.

Abstract: A ball game apparatus in which movements of a coded ball (20) are detected by detector units (100, 206) and an automatic indication of a player's score is given, where data relating to the ball (20) are stored in a database connected to the detector units (100, 206), the data including the code of a ball (20) and a code relating to a player to whom the ball (20) has been allocated, the ball (20) being configured to temporarily store, and to intermittently transfer to the detector units (100, 206) and thence to the database, data relating to the ball's movements. A rechargeable battery (40) is contained within the ball (20), and is arranged to be charged by a battery charging system. Features of the game may be controlled by means of a player's mobile telephone.

Abstract: Solution management systems and methods are presently disclosed that enable receiving, compiling, and analyzing vendor solutions, determining the vendor solutions that address a target vulnerability of a client network and/or client devices, determining additional vulnerabilities of the client network and/or client devices that the vendor solutions address, and selecting a vendor solution to remediate the target vulnerability. The presently disclosed systems and methods also enable scoring, risk evaluation, and additional metrics to facilitate determining the vendor solution(s) that have the largest impact and/or benefit to the various vulnerabilities of the client network and/or client devices.

Abstract: In one implementation, a circuit includes: a comparator; a shift register chain coupled to the comparator; and one or more converters coupled to respective shift registers of the shift register chain, wherein the one or more converters are configured to convert a source of current from a first voltage to a second voltage, and wherein the circuit is configured to selectively transmit an output signal to the one or more converters. In one implementation, the circuit is configured to selectively control modulation for the one or more converters.

Abstract: Described herein are single chain trimer (SCT) polypeptides comprising or consisting essentially of a target peptide, a first linker, at least a portion of a beta-2 microglobulin domain, a second linker, and at least a portion of a major histocompatibility complex (MHC) I alpha chain, or pharmaceutically acceptable derivatives thereof. The SCT polypeptides may further include a leader peptide, e.g., a PHO5, SUC2, app8, or HLA A2 leader sequence at the N-terminus of the target peptide. Further described herein are polypeptide compositions comprising or consisting essentially of a first polypeptide comprising a target peptide, and a second polypeptide comprising at least a portion of a beta-2 microglobulin domain, a second linker, and at least a portion of a major histocompatibility complex (MHC) I alpha chain, a third linker, and a tether peptide, or pharmaceutically acceptable derivatives thereof. The first polypeptide and/or the second polypeptide may further include a leader peptide, e.g.