Abstract: A method and structure for slots in wide lines to reduce stress. An example embodiment method and structure for is an interconnect structure comprising: interconnect comprising a wide line. The wide line has a first slot. The first slot is spaced a first distance from a via plug so that the first slot relieves stress on the wide line and the via plug. The via plug can contact the wide line from above or below. Another example embodiment is a dual damascene interconnect structure comprising: an dual damascene shaped interconnect comprising a via plug, a first slot and a wide line. The wide line has the first slot. The first slot is spaced a first distance from the via plug so that the first slot relieves stress on the wide line and the via plug.

Abstract: A method and structure for slots in wide lines to reduce stress. An example embodiment method and structure for is an interconnect structure comprising: interconnect comprising a wide line. The wide line has a first slot. The first slot is spaced a first distance from a via plug so that the first slot relieves stress on the wide line and the via plug. The via plug can contact the wide line from above or below. Another example embodiment is a dual damascene interconnect structure comprising: an dual damascene shaped interconnect comprising a via plug, a first slot and a wide line. The wide line has the first slot. The first slot is spaced a first distance from the via plug so that the first slot relieves stress on the wide line and the via plug.

Abstract: Methods of fabricating ultra-low power transistors are described using advanced technology nodes (e.g. 40 nm or less). In an embodiment, by optimizing a MOSFET to a different point, i.e. for low junction off (or leakage) current rather than speed/on current, a MOSFET can be produced which still meets the HCl reliability specification but has significantly reduced power consumption when off, e.g. half to one third of the standard off current. At this new optimisation point, the LDD dose is reduced to a level (e.g. 10-20% of the standard LDD dose) such that if it is reduced further, the device will no longer pass the HCl reliability specification. This is in contrast to standard MOSFETs which are optimized for speed/on current and have an LDD dose which, if increased further, would cause the device to no longer pass the HCl reliability specification.

Abstract: A drain extended MOS transistor configured to operate in a gate-depletion regime. Devices comprising such transistors are described together with fabrication processes for such devices and transistors.

Abstract: A drain extended MOS transistor configured to operate in a gate-depletion regime. Devices comprising such transistors are described together with fabrication processes for such devices and transistors.

Abstract: A drain extended MOS transistor configured to operate in a gate-depletion regime. Devices comprising such transistors are described together with fabrication processes for such devices and transistors.

Abstract: A MOS device, (400) comprising a semiconductor substrate comprising a channel, an electrode (402) insulated from the channel and positioned at least partly over the channel, and at least one contact (403) to the electrode, the at least one contact being positioned at least partly over the channel.

Abstract: A MOS device, (400) comprising a semiconductor substrate comprising a channel, an electrode (402) insulated from the channel and positioned at least partly over the channel, and at least one contact (403) to the electrode, the at least one contact being positioned at least partly over the channel.

Abstract: A drain extended MOS transistor configured to operate in a gate-depletion regime. Devices comprising such transistors are described together with fabrication processes for such devices and transistors.

Abstract: A one-time programmable (OTP) charge-trapping non-volatile memory (NVM) device is described. In an embodiment, an OTP transistor is formed using a thick gate oxide typically used in producing an I/O MOS transistor and source/drain extensions which are highly doped, shallow and include pocket implants and which are typically used in producing a CORE thin-oxide MOS transistor. In an optimization, the OTP transistor may be formed with two narrow active areas instead of one wider active area. This provides increased performance compared to a device with a wider active area and reduced variability compared to a device with one narrow active area. In another embodiment, a dual gate oxide CMOS technology provides three types of transistor; a thin oxide device, a thick oxide device, and a thick oxide device using the implant type of the thin oxide device for providing an OTP charge-trapping NVM device.

Abstract: A dual gate oxide CMOS technology providing three types of transistor; a thin oxide device, a thick oxide device, and a thin oxide device using the implant type of the thick oxide device for providing improved analogue performance.

Abstract: A new method to prevent cracking at the corners of a semiconductor die during dicing is described. Dummy metal structures are fabricated at the corners of the die to prevent cracking. The design for the dummy metal structures can be generated automatically by a computer program.

Abstract: A method of forming a double-gated transistor having a rounded active region to improve GOI and leakage current control comprises the following steps, inter alia. An SOI substrate is patterned and a rounded oxide layer is formed over the exposed side walls of a patterned upper SOI silicon layer. A dummy layer, having an opening defining a gate, is formed over the exposed patterned top oxide layer and the exposed portions of the upper SOI silicon layer. An undercut is formed into the undercut lower SOI oxide layer and the exposed gate area portion of the oxide layer is removed. The portion of the rounded oxide layer within the gate area is removed and a conformal oxide layer is formed over a part of the structure. A gate is formed within the second patterned dummy layer opening and the patterned dummy layer is removed to form the double gated transistor.

Abstract: A design, device, system and process for placing slots in active regions (e.g., metal areas). Embodiments of the present invention improve the planarization of metal areas (e.g., lines) and insulators by reducing depressions (e.g., dishing) in the metal areas by including symmetric or square slots inside selected wide metal lines, by adhering to a set of placement rules. Embodiments reduce dishing in copper dual damascene structures. Embodiments reduce data processing requirements for designing and arranging the layout of IC devices and the slots.

Abstract: A method and structure for slots in wide lines to reduce stress. An example embodiment method and structure for is an interconnect structure comprising: interconnect comprising a wide line. The wide line has a first slot. The first slot is spaced a first distance from a via plug so that the first slot relieves stress on the wide line and the via plug. The via plug can contact the wide line from above or below. Another example embodiment is a dual damascene interconnect structure comprising: an dual damascene shaped interconnect comprising a via plug, a first slot and a wide line. The wide line has the first slot. The first slot is spaced a first distance from the via plug so that the first slot relieves stress on the wide line and the via plug.

Abstract: A method of forming a double-gated transistor having a rounded active region to improve GOI and leakage current control comprises the following steps. An SOI substrate is patterned and a rounded oxide layer is formed over the exposed side walls of a patterned upper SOI silicon layer. A dummy layer, having an opening defining a gate, is formed over the exposed patterned top oxide layer and the exposed portions of the upper SOI silicon layer. An undercut is formed into the undercut lower SOI oxide layer and the exposed gate area portion of the oxide layer is removed. The portion of the rounded oxide layer within the gate area is removed and a conformal oxide layer is formed over a part of the structure. A gate is formed within the second patterned dummy layer opening and the patterned dummy layer is removed to form the double-gated transistor.

Abstract: A new method to prevent cracking at the corners of a semiconductor die during dicing is described. Dummy metal structures are fabricated at the corners of the die to prevent cracking. The design for the dummy metal structures can be generated automatically by a computer program.

Abstract: A method of forming a double-gated transistor having a rounded active region to improve GOI and leakage current control comprises the following steps, inter alia. An SOI substrate is patterned and a rounded oxide layer is formed over the exposed side walls of a patterned upper SOI silicon layer. A dummy layer, having an opening defining a gate, is formed over the exposed patterned top oxide layer and the exposed portions of the upper SOI silicon layer. An undercut is formed into the undercut lower SOI oxide layer and the exposed gate area portion of the oxide layer is removed. The portion of the rounded oxide layer within the gate area is removed and a conformal oxide layer is formed over a part of the structure. A gate is formed within the second patterned dummy layer opening and the patterned dummy layer is removed to form the double gated transistor.

Abstract: A method of forming a double-gated transistor having a rounded active region to improve GOI and leakage current control comprises the following steps, inter alia. An SOI substrate is patterned and a rounded oxide layer is formed over the exposed side walls of a patterned upper SOI silicon layer. A dummy layer, having an opening defining a gate, is formed over the exposed patterned top oxide layer and the exposed portions of the upper SOI silicon layer. An undercut is formed into the undercut lower SOI oxide layer and the exposed gate area portion of the oxide layer is removed. The portion of the rounded oxide layer within the gate area is removed and a conformal oxide layer is formed over a part of the structure. A gate is formed within the second patterned dummy layer opening and the patterned dummy layer is removed to form the double gated transistor.

Abstract: A method of forming a double gated SOI channel transistor comprising the following steps. A substrate having an SOI structure formed thereover is provided. The SOI structure including a lower SOI silicon oxide layer and an upper SOI silicon layer. The SOI silicon layer is patterned to form a patterned silicon layer. A dummy layer is formed over the SOI silicon oxide layer and the patterned SOI silicon layer. The dummy layer is patterned to form a damascene opening therein exposing: a portion of the lower SOI silicon oxide layer; and a central portion of the patterned SOI silicon layer to define a source structure and a drain structure. Patterning the exposed lower SOI silicon oxide layer to form a recess. Gate oxide layer portions are formed around the exposed portion of the patterned SOI silicon layer. A planarized layer portion is formed within the final damascene opening. The planarized layer portion including a bottom gate and a top gate.