Abstract: Provided is a method for protecting a program in an integrated circuit product. The method includes creating one or more opcode blocs to respectively replace one or more original opcodes of said program, said opcode bloc comprising a number of fictional opcodes and the corresponding original opcode, said fictional opcodes being to be executed without taking into account their results and without impacting an expected result of said program, said number and a position of the original opcode in said opcode bloc being randomly determined by a random or pseudo random number generator of said integrated circuit product, and executing said one or more opcode blocs.

Abstract: Provided is a method to secure against side channel attacks performing a cryptographic operation of a cryptographic algorithm. It includes selecting a multiplier integer t and determining a second integer q? by multiplying said first integer q, determining (S2) an invertible random polynomial R[X] in said first polynomial ring Rq, randomizing (S3) the coefficients Ai of said input polynomial A[X] based on said determined second integer q? and said determined random polynomial R[X], performing (S4) the polynomial operation of the cryptographic operation on said randomized input polynomials A?[X], and unmasking (S5) the result polynomial Res?(X) by applying to its coefficients a modulo said first integer q operation. Other embodiments disclosed.

Abstract: Provided is a method for securing against high-order side-channel attacks wherein a substep of field inversion is performed by a cryptographic device. The method includes computing (S1) a Dirac output value, adding (S2) said Dirac output value to one of said shares of the first set of shares to obtain a second set of shares, performing a conversion of the second set of shares (S3) from said (n+1) additive sharing to a (n+1)-multiplicative sharing, performing an inversion of each share of the (n+1)-multiplicative sharing (S4), performing a conversion of the inverted shares (S5) from said multiplicative sharing to a (n+1)-additive sharing to obtain a third set of shares, and adding (S6) said Dirac output value to one of said shares of the third set of shares. Other embodiments disclosed.

Abstract: Provided is a method for securing against side channel attacks. An elliptic curve cryptographic process comprises a multiple points multiplication operation using predetermined scalar values, Pi being points of an elliptic curve over a finite field defined by parameters (F, E, G, N) together with the point addition law where F is a field over which is defined the curve, E is an equation of the curve, G is a base point in E over F and N is the order of the base point G. The method comprises generating (S1) a masking value iRand, multiplicatively masking (S2) each predetermined scalar value di with said generated masking value iRand to obtain masked scalars di?, computing (S3) a masked multiple points multiplication operation result, and obtaining (S4) said multiple points multiplication operation result R by unmasking said masked multiple points multiplication operation result R?.

Abstract: Provided is a method for performing a cryptographic algorithm, performed by a cryptographic device comprising a cryptographic co-processor comprising an integer multiplier, said cryptographic algorithm comprising a polynomial multiplication between a first input polynomial A[X] and a second input polynomial B[X], wherein the first input polynomial A[X] and the second input polynomial B[X] comprise Nc coefficients and said coefficients of the first and second input polynomials are of size Nb bits, with Nc and Nb non-zero integers. A polynomial result is computed for a polynomial multiplication between said first input polynomial A[X] and said second input polynomial B[X] by generating (S11) a concatenated integer for each input polynomial as a concatenation of the coefficients of said input polynomial, each coefficient being extended to a size Ne with Ne??log2 Nc?+2*Nb by inserting zeros as Most Significant Bits of said concatenated coefficients. Other embodiments disclosed.

Abstract: A method for countering a profiling of deep-learning side channel (SCA) algorithm to disrupt a training phase of a deep-learning model is provided. It alters and interleaves an execution sequence of modular exponentiations or point additions in a counter SCA algorithm. The mixing, loops through bits of a private key, D, along a sliding window, wherein for each loop, an N-bit tuple from the private key is compared to the random number plus a linear increment, and, if the value is a match, it indexes into said precomputed vector according to said random number, r, thereby extracting and interleaving values into an execution path of said counter SCA algorithm from said precomputed vector according to an index represented by said random number; otherwise. Other embodiments are provided.

Abstract: Provided is a method to secure against side channel attacks performing a cryptographic operation of a cryptographic algorithm. It includes selecting a multiplier integer t and determining a second integer q? by multiplying said first integer q, determining (S2) an invertible random polynomial R[X] in said first polynomial ring Rq, randomizing (S3) the coefficients Ai of said input polynomial A[X] based on said determined second integer q? and said determined random polynomial R[X], performing (S4) the polynomial operation of the cryptographic operation on said randomized input polynomials A?[X], and unmasking (S5) the result polynomial Res?(X) by applying to its coefficients a modulo said first integer q operation. Other embodiments disclosed.

Abstract: Provided is a method for securing against side channel attacks. An elliptic curve cryptographic process comprises a multiple points multiplication operation using predetermined scalar values, Pi being points of an elliptic curve over a finite field defined by parameters (F, E, G, N) together with the point addition law where F is a field over which is defined the curve, E is an equation of the curve, G is a base point in E over F and N is the order of the base point G. The method comprises generating (S1) a masking value iRand, multiplicatively masking (S2) each predetermined scalar value di with said generated masking value iRand to obtain masked scalars di?, computing (S3) a masked multiple points multiplication operation result, and obtaining (S4) said multiple points multiplication operation result R by unmasking said masked multiple points multiplication operation result R?.

Abstract: Provided is a method for protecting a program in an integrated circuit product. The method includes creating one or more opcode blocs to respectively replace one or more original opcodes of said program, said opcode bloc comprising a number of fictional opcodes and the corresponding original opcode, said fictional opcodes being to be executed without taking into account their results and without impacting an expected result of said program, said number and a position of the original opcode in said opcode bloc being randomly determined by a random or pseudo random number generator of said integrated circuit product, and executing said one or more opcode blocs.

Abstract: Provided is a method for securing against high-order side-channel attacks wherein a substep of field inversion is performed by a cryptographic device. The method includes computing (S1) a Dirac output value, adding (S2) said Dirac output value to one of said shares of the first set of shares to obtain a second set of shares, performing a conversion of the second set of shares (S3) from said (n+1) additive sharing to a (n+1)-multiplicative sharing, performing an inversion of each share of the (n+1)-multiplicative sharing (S4), performing a conversion of the inverted shares (S5) from said multiplicative sharing to a (n+1)-additive sharing to obtain a third set of shares, and adding (S6) said Dirac output value to one of said shares of the third set of shares. Other embodiments disclosed.

Abstract: The present invention relates to a computing device for executing a first cryptographic operation of a cryptographic process on useful input data, said computing device comprising a first processor, a second processor and a selection circuit wherein: —said selection circuit is configured: —for receiving, from an input bus, expanded input data obtained by interleaving dummy input data with said useful input data, —for determining positions of the dummy input data in said expanded input data, —and for extracting said dummy input data and said useful input data from the expanded input data based on said determined positions, —said first processor is configured for executing said first cryptographic operation of said cryptographic process on said extracted useful input data to obtain useful output data, —said second processor is configured for executing a second operation on said extracted dummy input data to obtain dummy output data, said computing device being configured for having said operations executed such

Abstract: Provided is a method for securing against fault attacks during verification a digital signature of a message on a client device. It performs (S1) at least one check on intermediate parameters that are generated for one that is different from 0 modulo n. It checks that values computed by several executions of the verification algorithm are the same, and checks that at least one mathematical relationship is verified. It performs a signature comparison final step to test equality between one of the intermediate parameters and a part of the digital signature. It triggers (S2) a fault attack countermeasure when at least one of the performed checks has failed.

Abstract: The present invention relates to a method secured against side channel attacks performing an arithmetic operation of a cryptographic algorithm mixing Boolean and arithmetic operations, wherein said method is performed by a cryptographic device comprising a processing system having at least one hardware processor, and said operation has a first value (x) and a second value (y) as operands, comprising: —obtaining (S1) a first masked value (x?), a second masked value (y?), a first Boolean mask (rx), a second Boolean mask (ry), said first masked value (x?) resulting from masking said first value (x) by said first Boolean mask (rx) by performing a Boolean exclusive OR (XOR) operation between said first value (x) and said first Boolean mask (rx), and said second masked value (y?) resulting from masking said second value (y) by said second Boolean mask (ry) by performing a Boolean exclusive OR (XOR) operation between said second value (y) and said second Boolean mask (ry), —performing (S2) in any order a plurality o

Abstract: The present invention relates to a method for securing against N-order side-channel attacks a cryptographic process using in a plurality of encryption rounds an initial Substitution box S0 comprising the steps of: —generating (E12) a first randomized substitution box S1 by masking said initial substitution box S0 such that S1(x XOR m1)=S0(x) XOR m2, with m1, m2 uniformly-distributed random values, for any input value x of the initial substitution box S0, —generating (E13) a first transrandomized Substitution box S(1,1) from the first randomized substitution box S1 and from masks m1,1, m?1,1 such that S(1, 1)[x]=S1[x xor (m1 xor m1,1)] xor (m2 xor m?1,1) for any input value x of the first transrandomized Substitution box S(1,1), —generating (E14) from the first transrandomized Substitution box S(1,1) a N?1th transrandomized Substitution box S(1, N?1) by performing iteratively N?2 times a step of generation of a ith transrandomized Substitution box S(1, i) from a i?1th transrandomized substitution box S(1, i?1)

Abstract: The present invention relates to a computing device for executing a first cryptographic operation of a cryptographic process on useful input data, said computing device comprising a first processor, a second processor and a selection circuit wherein: said selection circuit is configured: for receiving, from an input bus, expanded input data obtained by interleaving dummy input data with said useful input data, for determining positions of the dummy input data in said expanded input data, and for extracting said dummy input data and said useful input data from the expanded input data based on said determined positions, said first processor is configured for executing said first cryptographic operation of said cryptographic process on said extracted useful input data to obtain useful output data, said second processor is configured for executing a second operation on said extracted dummy input data to obtain dummy output data, said computing device being configured for having said operations executed such that

Abstract: The present invention relates to a method secured against side channel attacks performing an arithmetic operation of a cryptographic algorithm mixing Boolean and arithmetic operations, wherein said method is performed by a cryptographic device comprising a processing system having at least one hardware processor, and said operation has a first value (x) and a second value (y) as operands, comprising:—obtaining (S1) a first masked value (x?), a second masked value (y?), a first Boolean mask (rx), a second Boolean mask (ry), said first masked value (x?) resulting from masking said first value (x) by said first Boolean mask (rx) by performing a Boolean exclusive OR (XOR) operation between said first value (x) and said first Boolean mask (rx), and said second masked value (y?) resulting from masking said second value (y) by said second Boolean mask (ry) by performing a Boolean exclusive OR (XOR) operation between said second value (y) and said second Boolean mask (ry),—performing (S2) in any order a plurality of

Abstract: A system, method and computer-readable storage medium with instructions for protecting an electronic device against fault attack. Given a data represented as an input codeword of a systematic linear error correcting code, the technology provides the secure computation of the output codeword corresponding to the result of the non-linear function applied to this data. Other systems and methods are disclosed.

Abstract: The present invention relates to a method for securing against N-order side-channel attacks a cryptographic process using in a plurality of encryption rounds an initial Substitution box S0 comprising the steps of: —generating (E12) a first randomized substitution box S1 by masking said initial substitution box S0 such that S1(x XOR m1)=S0(x) XOR m2, with m1, m2 uniformly-distributed random values, for any input value x of the initial substitution box S0, —generating (E13) a first transrandomized Substitution box S(1,1) from the first randomized substitution box S1 and from masks m1,1, m?1,1 such that S(1, 1)[x]=S1[x xor (m1 xor m1,1)] xor (m2 xor m?1,1) for any input value x of the first transrandomized Substitution box S(1,1), —generating (E14) from the first transrandomized Substitution box S(1,1) a N?1th transrandomized Substitution box S(1, N?1) by performing iteratively N?2 times a step of generation of a ith transrandomized Substitution box S(1, i) from a i?1th transrandomized substitution box S(1, i?1)

Abstract: A system, method and computer-readable storage medium with instructions for protecting an electronic device against fault attack. The technology includes operating the electronic device to determine two half-size exponents, dp and dq, from the exponent d; to split the base m into two sub-bases mp and mq determined from the base m; and to iteratively compute a decryption result S by repeatedly multiplying an accumulator A by m, mp, mq or 1 depending on the values of the i-th bit of dp and dq for each iteration I?. Other systems and methods are disclosed.

Abstract: A system, method and computer-readable storage medium with instructions for protecting an electronic device against fault attack. Given a data represented as an input codeword of a systematic linear error correcting code, the technology provides the secure computation of the output codeword corresponding to the result of the non-linear function applied to this data. Other systems and methods are disclosed.