Abstract: A chip-to-chip integration process for rapid prototyping of silicon avalanche photodiode (APD) arrays has been developed. This process has several advantages over wafer-level 3D integration, including: (1) reduced cost per development cycle since a dedicated full-wafer read-out integrated circuit (ROIC) fabrication is not needed, (2) compatibility with ROICs made in previous fabrication runs, and (3) accelerated schedule. The process provides several advantages over previous processes for chip-to-chip integration, including: (1) shorter processing time as the chips can be diced, bump-bonded, and then thinned at the chip-level faster than in a wafer-level back-illumination process, and (2) the CMOS substrate provides mechanical support for the APD device, allowing integration of fast microlenses directly on the APD back surface. This approach yields APDs with low dark count rates (DCRs) and higher radiation tolerance for harsh environments and can be extended to large arrays of APDs.

Abstract: A chip-to-chip integration process for rapid prototyping of silicon avalanche photodiode (APD) arrays has been developed. This process has several advantages over wafer-level 3D integration, including: (1) reduced cost per development cycle since a dedicated full-wafer read-out integrated circuit (ROIC) fabrication is not needed, (2) compatibility with ROICs made in previous fabrication runs, and (3) accelerated schedule. The process provides several advantages over previous processes for chip-to-chip integration, including: (1) shorter processing time as the chips can be diced, bump-bonded, and then thinned at the chip-level faster than in a wafer-level back-illumination process, and (2) the CMOS substrate provides mechanical support for the APD device, allowing integration of fast microlenses directly on the APD back surface. This approach yields APDs with low dark count rates (DCRs) and higher radiation tolerance for harsh environments and can be extended to large arrays of APDs.

Abstract: A method of forming fiber arrays includes using a base substrate to form an alignment pattern, holding a fiber fixed with reference to the pattern, and, while the fiber is held fixed, bonding a cap to the fiber, the cap being of a material having a different coefficient of thermal expansion than the base substrate. The base substrate can be an etched silicon chip and the cap can be of a fused silicon material. The method provides one and two dimensional arrays of fibers, the fiber aligning structures of the arrays having coefficients of thermal expansion selected to match those of connecting components. A fiber array made by the method includes a pair of substrates, a fiber sandwiched between the substrates, and a molded material holding the fiber in a predetermined alignment with respect to a pattern preformed in the molded material.

Abstract: A method for polishing a substrate having at least one micro-sized structure. The method includes identifying a first region of the substrate on which a micro-sized structure is to be located. The first region is the region in which polishing is desired. A second region of the substrate, in which polishing is not desired, is also identified. An adhesion promoter is optionally applied to the substrate. The second region of the substrate is coated with a selected coating material that does not degrade substantially when exposed to a selected electrolyte. Material is removed from the first region, exposing a micro-sized structure. The coating material may be removed by the same machining process that forms the micro-sized structure. The substrate is submerged in the selected electrolyte so that the first region is exposed to the electrolyte. The first region of the substrate is electropolished. The coating is then optionally removed.

Abstract: A multi-layer interconnect structure of alternating dielectric (e.g., polyimide) and metal (e.g., copper) is built on a substrate supporting a continuous layer of metal. This metal layer is used as an electrode for plating vias through all the dielectric layers. Once the desired number of layers are formed, the substrate is removed and the continuous metal layer is patterned. Solid metal vias having nearly vertical side walls can be stacked vertically, producing good electrical and thermal transfer paths and permitting small, closely-spaced conductors. Further, by mixing geometrical shapes of conductors, a variety of useful structures can be achieved, such as controlled impedance transmission lines and multiconductor TAB tape with interconnects on tape of different dimensions than TAB fingers.

Abstract: A multi-layer interconnect structure of alternating dielectric (e.g., polyimide) and metal (e.g., copper) is built on a substrate supporting a continuous layer of metal. This metal layer is used as an electrode for plating vias through all the dielectric layers. Once the desired number of layers are formed, the substrate is removed and the continuous metal layer is patterned. Solid metal vias having nearly vertical side walls can be stacked vertically, producing good electrical and thermal transfer paths and permitting small, closely-spaced conductors. Further, by mixing geometrical shapes of conductors, a variety of useful structures can be achieved, such as controlled impedance transmission lines and multiconductor TAB tape with interconnects on tape of different dimensions than TAB fingers.