Patents by Inventor David W. Boggs
David W. Boggs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120219145Abstract: A system and method for providing microphonic isolation on a transmission line. The transmission line has a first part and a second part. The first part of transmission line carries a data signal and a microphonic signal. The microphonic signal has frequencies that include those in a range of substantially 20 Hz to substantially 20 kHz. The system includes an isolation apparatus. The isolation apparatus has an input in electrical communication with a first part of the transmission line, an output in electrical communication with the second part of the transmission line, and a filter in electrical communication with the input and the output. The filter is arranged to substantially remove the microphonic signal received at the input from first part of transmission line and pass the data signal to the output.Type: ApplicationFiled: May 9, 2012Publication date: August 30, 2012Applicant: AVAYA INC.Inventors: David S.J. RENDER, Marc SAUNDERS, Dennis POTHIER, Phillip R. RUTTAN, David W. BOGGS
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Publication number: 20120201398Abstract: A system and method for providing microphonic isolation on a transmission line. The transmission line has a first part and a second part. The first part of transmission line carries a data signal and a microphonic signal. The microphonic signal has frequencies that include those in a range of substantially 20 Hz to substantially 20 kHz. The system includes an isolation apparatus. The isolation apparatus has an input in electrical communication with a first part of the transmission line, an output in electrical communication with the second part of the transmission line, and a filter in electrical communication with the input and the output. The filter is arranged to substantially remove the microphonic signal received at the input from first part of transmission line and pass the data signal to the output.Type: ApplicationFiled: April 23, 2012Publication date: August 9, 2012Applicant: AVAYA INC.Inventors: David S.J. RENDER, Marc SAUNDERS, Dennis POTHIER, Phillip R. RUTTAN, David W. BOGGS
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Patent number: 8199922Abstract: A system and method for providing microphonic isolation on a transmission line. The transmission line has a first part and a second part. The first part of transmission line carries a data signal and a microphonic signal. The microphonic signal has frequencies that include those in a range of substantially 20 Hz to substantially 20 kHz. The system includes an isolation apparatus. The isolation apparatus has an input in electrical communication with a first part of the transmission line, an output in electrical communication with the second part of the transmission line, and a filter in electrical communication with the input and the output. The filter is arranged to substantially remove the microphonic signal received at the input from first part of transmission line and pass the data signal to the output.Type: GrantFiled: November 21, 2008Date of Patent: June 12, 2012Assignee: Avaya Inc.Inventors: David S. J. Render, Marc Saunders, Dennis Pothier, Philip R. Ruttan, David W. Boggs
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Patent number: 7583513Abstract: A device includes a plane metallization layer, and a plane plated through hole attached to the plane metallization layer and terminating at the at a major exterior surface with a plurality of component mounting pads. The plated through hole is attached to the plane metallization layer. The plane plated through hole is electrically isolated from the plurality of component mounting pads at the exterior surface. A method for testing the device includes contacting the signal carrying through hole, and contacting the plane through hole, and checking for current flow between the signal carrying through hole and the plane through hole. If current flows between the signal carrying through hole and the plane through hole the device fails. If no current flows between the signal carrying through hole and the plane through hole the device passes.Type: GrantFiled: September 23, 2003Date of Patent: September 1, 2009Assignee: Intel CorporationInventors: David W Boggs, John H Dungan, Daryl A Sato
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Publication number: 20090161884Abstract: A system and method for providing microphonic isolation on a transmission line. The transmission line has a first part and a second part. The first part of transmission line carries a data signal and a microphonic signal. The microphonic signal has frequencies that include those in a range of substantially 20 Hz to substantially 20 kHz. The system includes an isolation apparatus. The isolation apparatus has an input in electrical communication with a first part of the transmission line, an output in electrical communication with the second part of the transmission line, and a filter in electrical communication with the input and the output. The filter is arranged to substantially remove the microphonic signal received at the input from first part of transmission line and pass the data signal to the output.Type: ApplicationFiled: November 21, 2008Publication date: June 25, 2009Applicant: NORTEL NETWORKS LIMITEDInventors: David S.J. RENDER, Marc SAUNDERS, Dennis POTHIER, Phillip R. RUTTAN, David W. BOGGS
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Patent number: 7385288Abstract: Formation of a plurality of conductive connectors of an integrated circuit package is described. The conductive connectors made with a conductive elastomer material and formed using an interposer that includes a plurality of the conductive connectors linked together.Type: GrantFiled: June 11, 2007Date of Patent: June 10, 2008Assignee: Intel CorporationInventors: David W. Boggs, John H. Dungan, Frank A. Sanders, Daryl A. Sato, Dan Willis
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Patent number: 7325303Abstract: A generally planar interposer having a plurality of interposer contact pads to contact a plurality of first contacts of a first electronic device on one side of the interposer, and a plurality of electrical connections between the interposer contact pads and a plurality of pressure contacts on the other side of the interposer. Each of the pressure contacts having a directionally deformable contact surface to removably contact a plurality of second contacts of a second electronic device on the other side of the interposer. Also methods of forming the interposer.Type: GrantFiled: December 8, 2006Date of Patent: February 5, 2008Assignee: Intel CorporationInventors: David W. Boggs, John H. Dungan, Frank A. Sanders, Daryl A. Sato, Dan Willis
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Patent number: 7241680Abstract: Formation of a plurality of conductive connectors of an integrated circuit package is described. The conductive connectors made with a conductive elastomer material and formed using an interposer that includes a plurality of the conductive connectors linked together.Type: GrantFiled: April 30, 2004Date of Patent: July 10, 2007Assignee: Intel CorporationInventors: David W. Boggs, John H. Dungan, Frank A. Sanders, Daryl A. Sato, Dan Willis
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Patent number: 7201583Abstract: A generally planar interposer having a plurality of interposer contact pads to contact a plurality of first contacts of a first electronic device on one side of the interposer, and a plurality of electrical connections between the interposer contact pads and a plurality of pressure contacts on the other side of the interposer. Each of the pressure contacts having a directionally deformable contact surface to removably contact a plurality of second contacts of a second electronic device on the other side of the interposer. Also methods of forming the interposer.Type: GrantFiled: December 31, 2003Date of Patent: April 10, 2007Assignee: Intel CorporationInventors: David W. Boggs, John H. Dungan, Frank A. Sanders, Daryl A. Sato, Dan Willis
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Patent number: 7147141Abstract: A method for providing an improved solder joint for a via-in-pad ball grid array package. One or more bonding pads are formed upon a substrate. One or more vias are formed through the substrate within the bonding pad. The vias are plugged with a via plug material. The via plug material is then preconditioned such that an amount of volatiles within the via plug material is reduced.Type: GrantFiled: November 13, 2002Date of Patent: December 12, 2006Assignee: Intel CorporationInventors: Daryl Sato, Gary Paek, John Dungan, David W. Boggs
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Patent number: 7084354Abstract: An electronic assembly is disclosed. The electronic assembly includes a lower portion and a first elongate trace formed on an upper surface of the lower portion. The trace is covered by an upper portion, and an opening formed through an upper surface of the upper portion extends to the trace to expose a portion of the trace. A second elongate trace is formed on the upper portion. A portion of the second elongate trace positioned in the opening formed through the upper surface of the upper portion contacts the first elongate trace through the opening to form an electrical interconnection between the first trace and the second trace.Type: GrantFiled: June 14, 2002Date of Patent: August 1, 2006Assignee: Intel CorporationInventors: David W. Boggs, Daryl A. Sato, John H. Dungan, Gary I. Paek
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Patent number: 7061116Abstract: An arrangement of pads with selective via in pad for mounting a semiconductor package on a substrate. In order to strengthen the soldered bonds, standard pads, which have a stronger bond, are used in locations of greatest stress and deflection. Vias in pad (VIP) are used at all other locations to improve routing advantages due to their smaller surface area.Type: GrantFiled: September 26, 2001Date of Patent: June 13, 2006Assignee: Intel CorporationInventors: Carolyn McCormick, Rebecca Jessep, John Dungan, David W. Boggs, Daryl Sato
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Patent number: 7061095Abstract: A printed circuit board and a system and method of embedding conductor channels into a printed circuit board. These conductor channels are used to provided increased power to circuits on the printed circuit board, provide shielding for these circuits and provide communications for these circuits. These conductor channels are created by ablating dielectric layers in the printed circuit board and depositing a conductive material therein.Type: GrantFiled: September 26, 2001Date of Patent: June 13, 2006Assignee: Intel CorporationInventors: David W. Boggs, Rebecca Jessep, Carolyn McCormick, Daryl Sato
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Patent number: 6941537Abstract: A standoff device provides predetermined control of a standoff distance between electrical components mounted together with opposing conductive grid array patterns. In an embodiment, a predetermined electrical function is provided by the device to at least one of the electrical components. The standoff device comprises a plurality of rigid one-piece standoff pins which, in an embodiment, contains one or more stops which buttress against the electrical components to serve as a distancing control structure. In an embodiment, the standoff device is integral with one of the electrical components.Type: GrantFiled: February 7, 2002Date of Patent: September 6, 2005Assignee: Intel CorporationInventors: Rebecca A. Jessep, David W. Boggs, Carolyn McCormick, John H. Dungan, Daryl A. Sato
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Publication number: 20040231886Abstract: An apparatus and method for providing a vented blind via in pad of a printed circuit board (PCB). A vent in the blind via in pad to allow gases formed during reflow soldering to escape from the solder joint. In one embodiment, the vent extends from the outer edge of the pad to the blind via. In another embodiment, a method includes forming a blind via in pad having a vent.Type: ApplicationFiled: June 17, 2004Publication date: November 25, 2004Inventors: David W. Boggs, John H. Dungan, Gary I. Paek, Daryl A. Sato
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Publication number: 20040219342Abstract: An electronic substrate for interconnecting electronic components comprises a substrate having one or more conductive inner layers and one or more interconnect cavities extending into the substrate to expose one or more of the inner layers.Type: ApplicationFiled: December 31, 2003Publication date: November 4, 2004Inventors: David W. Boggs, Daryl A. Sato, John H. Dungan, Gary Paek
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Patent number: 6787443Abstract: An apparatus and method for providing a vented blind via in pad of a printed circuit board (PCB). A vent in the blind via in pad to allow gases formed during reflow soldering to escape from the solder joint. In one embodiment, the vent extends from the outer edge of the pad to the blind via. In another embodiment, a method includes forming a blind via in pad having a vent.Type: GrantFiled: May 20, 2003Date of Patent: September 7, 2004Assignee: Intel CorporationInventors: David W. Boggs, John H. Dungan, Gary I. Paek, Daryl A. Sato
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Publication number: 20040129453Abstract: Embodiments of substrate in accordance with the present invention provide interconnect cavities for direct interconnection between SMT components and internal conductive inner layers, as well as surface outer layers. Interconnect cavities eliminate the need for through hole vias and require less substrate surface area and internal volume. Each interconnect cavity comprises a cavity extending from the substrate surface to an adjacent internal conductive inner layer directly beneath the cavity. The cavity extends through a conductive outer layer on the substrate surface. The cavity has a conductive liner interconnected with the outer layer and the inner layer forming a cup-shaped conductive depression interconnecting the outer layer with the inner layer.Type: ApplicationFiled: January 7, 2003Publication date: July 8, 2004Inventors: David W. Boggs, Daryl Sato, John Dungan
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Publication number: 20040089700Abstract: A method for providing an improved solder joint for a via-in-pad ball grid array package. One or more bonding pads are formed upon a substrate. One or more vias are formed through the substrate within the bonding pad. The vias are plugged with a via plug material. The via plug material is then preconditioned such that an amount of volatiles within the via plug material is reduced.Type: ApplicationFiled: November 13, 2002Publication date: May 13, 2004Inventors: Daryl Sato, Gary Paek, John Dungan, David W. Boggs
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Patent number: 6667090Abstract: A registration coupon is provided for a printed circuit board or other substrate. The registration coupon may be used to determine a hole-to-outer layer feature registration and a solder mask registration. The registration coupon may include a registration hole provided on the circuit board, a metal pad and an anti-pad provided on the circuit board about the registration hole, and a solder mask covering the metal pad.Type: GrantFiled: September 26, 2001Date of Patent: December 23, 2003Assignee: Intel CorporationInventors: David W. Boggs, Rebecca A. Jessep, Carolyn McCormick, Daryl A. Sato, John H. Dungan