Patents by Inventor David W. Bruneau

David W. Bruneau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Sense amplifier having reduced Vt mismatch in input matched differential pair
    Patent number: 6566914
    Abstract: A sense amplifier in which its output nodes provide a full voltage swing between the supply and return nodes. The sense amplifier further includes a reset circuit to selectively equalize the first and second output nodes. An output of the sense amplifier is coupled to either a digital logic gate or a flip-flop to receive the full swing. Each field effect transistor (FET) of the input pair in the sense amplifier is either zero body biased or forward body biased, so that a bulk-source junction of each FET is either zero biased or forward biased.
    Type: Grant
    Filed: June 26, 2002
    Date of Patent: May 20, 2003
    Assignee: Intel Corporation
    Inventors: David W. Bruneau, Siva G. Narendra, Vivek K. De
  • Sense amplifier having reduced Vt mismatch in input matched differential pair
    Publication number: 20020167340
    Abstract: A sense amplifier in which its output nodes provide a full voltage swing between the supply and return nodes. The sense amplifier further includes a reset circuit to selectively equalize the first and second output nodes. An output of the sense amplifier is coupled to either a digital logic gate or a flip-flop to receive the full swing. Each field effect transistor (FET) of the input pair in the sense amplifier is either zero body biased or forward body biased, so that a bulk-source junction of each FET is either zero biased or forward biased.
    Type: Application
    Filed: June 26, 2002
    Publication date: November 14, 2002
    Inventors: David W. Bruneau, Siva G. Narendra, Vivek K. De
  • FORWARD BODY BIAS GENERATION CIRCUITS BASED ON DIODE CLAMPS
    Publication number: 20020163377
    Abstract: Various embodiments of a method for providing forward body bias (FBB) are disclosed. A first diode element is forward biased to a first voltage. A voltage proportional to the first diode voltage is converted into a current. A current is mirrored through a second diode element to generate a second diode voltage. A constant FBB based upon the second diode voltage is generated and applied to each bulk terminal of field effect transistors (FETs) of an integrated circuit die.
    Type: Application
    Filed: March 28, 2001
    Publication date: November 7, 2002
    Inventors: David W. Bruneau, Siva G. Narendra, Vivek K. De
  • Forward body bias generation circuits based on diode clamps
    Patent number: 6469572
    Abstract: Various embodiments of a method for providing forward body bias (FBB) are disclosed. A first diode element is forward biased to a first voltage. A voltage proportional to the first diode voltage is converted into a current. A current is mirrored through a second diode element to generate a second diode voltage. A constant FBB based upon the second diode voltage is generated and applied to the bulk terminal of a field effect transistor (FET) of an integrated circuit die.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: October 22, 2002
    Assignee: Intel Corporation
    Inventors: David W. Bruneau, Siva G. Narendra, Vivek K. De
  • Sense amplifier having reduced Vt mismatch in input matched differential pair
    Patent number: 6445216
    Abstract: A sense amplifier in which its output nodes provide a full voltage swing between the supply and return nodes. The sense amplifier further includes a reset circuit to selectively equalize the first and second output nodes. An output of the sense amplifier is coupled to either a digital logic gate or a flip-flop to receive the full swing. Each field effect transistor (FET) of the input pair in the sense amplifier is either zero body biased or forward body biased, so that a bulk-source junction of each FET is either zero biased or forward biased.
    Type: Grant
    Filed: May 14, 2001
    Date of Patent: September 3, 2002
    Assignee: Intel Corporation
    Inventors: David W. Bruneau, Siva G. Narendra, Vivek K. De
  • Robust forward body bias generation circuit with digital trimming for DC power supply variation
    Patent number: 6429726
    Abstract: A method and apparatus provide a forward body bias (FBB) according to various embodiments, in which a supply voltage is divided into a number of dc voltages. One of these voltages is selected as a function of the supply voltage (as measured between a power supply line and a power return line). A constant FBB is generated based upon the selected dc voltage and applied to each bulk terminal of at least some of the field effect transistors (FETs) of a given conductivity type in a functional unit block (FUB) of an integrated circuit die.
    Type: Grant
    Filed: March 27, 2001
    Date of Patent: August 6, 2002
    Assignee: Intel Corporation
    Inventors: David W. Bruneau, Siva G. Narendra, Vivek K. De