Abstract: A program voltage is applied to the drain electrode of a floating gate transistor to program the floating gate transistor. Concurrent with the application of the program voltage, a current based on the voltage at the source electrode of the floating gate transistor is compared with a threshold current to verify the programming of the floating gate transistor. When the bit cell current falls below the threshold current, the floating gate transistor is considered to be sufficiently programmed and the next floating gate transistor to be programmed is selected. Further, the program voltage supply emulates the selection circuitry used to select between the bit cells so as to model the voltage drop caused by the selection circuitry between the program voltage supply and the drain electrode of the floating gate transistor being programmed. The program voltage supply adjusts the output program voltage based on the modeled voltage drop.

Abstract: A method and apparatus for random-access scan of a network 990 of dynamic logic or N-NARY logic that includes sequentially clocked precharge logic gates and one or more scan gates (900) driven by multiple overlapping clock signals generated from a clock generation circuit (904) coupled to a clock spine (902). Each clocked precharge logic gate and each scan gate include a logic tree (502) with one or more evaluate nodes, a precharge circuit (32), an evaluate circuit (36), and one or more output buffers (34). Each scan gate further includes a scan circuit (806) that accepts scan control signals (406, 408, 410, 824, and 826) and couples to one or more scan registers (416) in a RAM-like architecture. Scan control signals operate to capture the state of the output buffers of the scan gate, and to force the output buffers of the scan gate to a preselected level.

Abstract: A method and apparatus for random-access scan of a network 990 of dynamic logic or N-NARY logic that includes sequentially clocked precharge logic gates and one or more scan gates (900) driven by multiple overlapping clock signals generated from a clock generation circuit (904) coupled to a clock spine (902). Each clocked precharge logic gate and each scan gate include a logic tree (502) with one or more evaluate nodes, a precharge circuit (32), an evaluate circuit (36), and one or more output buffers (34). Each scan gate further includes a scan circuit (806) that accepts scan control signals (406, 408, 410, 824, and 826) and couples to one or more scan registers (416) in a RAM-like architecture. Scan control signals operate to capture the state of the output buffers of the scan gate, and to force the output buffers of the scan gate to a preselected level.

Abstract: A floating-gate non-volatile memory (30) uses a relatively-low threshold voltage to define a programmed state. The memory (30) compensates for fast program cells by providing program pulses which increase in length and magnitude while the cells are being programmed. Between each program pulse the memory (30) determines whether selected cells have been adequately programmed. The memory (30) ceases applying the series of pulses to each cell when it has been adequately programmed. Thus the memory (30) avoids the over-program condition instead of compensating for it.

Abstract: A charge pump with controlled ramp rate (200) includes a charge pump (65), an RC differentiator circuit (258), and a trigger circuit (238). The charge pump (65) receives a clock signal and provides a high output voltage for programming and erasing an EEPROM. The RC differentiator circuit (258) provides a control voltage that is proportional to the ramp-up rate of the high output voltage. The trigger circuit (238) receives the control voltage, and provides a control signal to disable the charge pump (65) if the ramp-up rate exceeds a predetermined rate. When the ramp-up rate falls below the predetermined rate, the trigger circuit (238) provides a control signal to enable the charge pump (65). The trigger circuit (238) has hysteresis to regulate its switching point. Controlling the ramp-up rate of the output voltage reduces the peak tunneling current in the EEPROM cell to increase reliability.