Abstract: A method of detecting misrouted inter-office transport facility routes in a telecommunications system is disclosed. The method includes receiving a plurality of provisioning orders corresponding to a plurality of newly requested inter-office facility routes to be added to the telecommunications system, and comparing the plurality of newly requested inter-office facility routes to a plurality of preferred routes that have been stored in a preferred routes database to identify a first set of routes that match the preferred routes, a second set of misrouted routes where a preferred route has been defined and previously stored, but where the newly requested route does not match the preferred route, and a third set of unmatched routes where a preferred route has not been previously stored in the preferred routes database.

Abstract: An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns.

Abstract: An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns.

Abstract: An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patters to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns.

Abstract: A mixed signal integrated circuit testing system includes a system controller connected to a test head for controlling the testing operations of the mixed signal integrated circuit testing system. The test head is adapted to support a wide combination of both the analog and digital circuit testing modules. A DUT board, typically configured for a specific IC or family of ICs, is used to connect the circuit testing modules to the IC. The DUT board is connected to a DUT board interface that includes an analog DUT board interface adapter and a digital DUT board interface adapter. The digital DUT board interface adapter is connected directly to the digital circuit testing modules. The analog DUT board interface adapter is connected to a system configuration module that provides analog loading and conditioning circuitry as well as other circuitry that can be customized for testing specific ICs.

Abstract: The present invention is a putter head having a rear face, a ball striking face, a heel area, a toe area, an upper area and a lower area. An attaching device is secured to the upper area to enable a conventional shaft to be secured thereto. Extending through the rear face and between the heel area and toe area is a cavity. The upper area of the cavity is smaller in size than the lower area of the cavity. The putter includes a sole having six planes. The six planes are equally proportioned planes of the sole and will release one quarter of one inch from a centerline of the lower area. This will provide for an overspin being imparted on the ball soon after impact. This will innately result in a truer roll and less margin for error in the ball rolling on line to the hole.

Abstract: A sealable enclosure including a base and a cover attachable to the base, the base and cover have respective mating surfaces, wherein the base and cover form a chamber there between when the cover is attached to the base. A compliant gel sealant is disposed on the mating surface of one of the base and cover for environmentally sealing the chamber, with a visual indicator provided for determining that the chamber is sealed. In one preferred embodiment, the visual indicator comprises a non-opaque window formed in the cover, and a non-opaque tongue extending from the mating surface of the cover, the tongue aligned with the window such that a line of sight is provided through the respective window and tongue.

Abstract: An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns.

Abstract: An interface system interconnects a common power supply and plural data communications paths located in a safe environment to a plurality of load devices located in a flammable atmosphere. A module power attenuator attenuates the electrical power output level of the common power supply to a first predetermined level for application to the load devices. A digital signal attenuator attenuates the electrical power level between data communications paths to a second predetermined level for application to the load devices. Coupling devices are utilized to maintain electrical segregation but allow communication to and from the safe environment.