Abstract: The invention relates to detecting vulnerabilities in technology infrastructure environments. Data describing vulnerabilities detected in a technological environment of an enterprise is obtained. The vulnerability data is combined with data relating to servers, applications associated with the servers, and business functions associated with the applications, within the technological environment of the enterprise in order to create enriched data. The enriched data is enhanced using one or more of the following proceses: deduplicating records in the enriched data; modifying of a severity assigned to vulnerabilities based on one or more enterprise-infrastructure factors; archiving and purging of records included in the enriched data; consolidating IP addresses associated with the vulnerabilities; excepting records in the enriched data for vulnerabilities undergoing active remediation; and validating the enriched data. After the enriched data is enhanced, it may be sorted in accordance with one or more filters.

Abstract: An apparatus for aligning a mask having an image and at least one complimentary alignment mark to a substrate having a first surface and a substantially opposing second surface. The substrate further has at least one alignment mark on the second surface. A mask support supports the mask in proximity to the first surface of the substrate. A substrate support supports the substrate with the first surface in proximity to the mask. An alignment means aligns the at least one alignment mark on the second surface of the substrate to the at least one complimentary alignment mark on the mask. An exposure source projects the image of the mask onto the first surface of the substrate, and a controller controls the mask support, substrate support, alignment means, and exposure source.

Abstract: An apparatus for monitoring the condition of a lubricating medium includes a UV light source, a UV receiver, a processor electrically coupled to both the UV light source and the UV receiver, and a memory device electrically coupled to the processor. The memory device has stored therein a plurality of instructions which, when executed by the processor, cause the processor to (a) communicate with the UV light source and the UV receiver so as to expose a sample of the lubricating medium to the UV light and generate a UV spectrum of the sample in response thereto, and (b) compare the UV spectrum of the sample to a model spectrum and generate a control signal if the UV spectrum of the sample has a predetermined relationship to the model spectrum.

Abstract: An integrated circuit substrate having a first surface for receiving a series of aligned layers during the creation of the integrated circuit, and a second surface disposed substantially opposite the first surface, where the second surface has at least one alignment mark for aligning the series of aligned layers one to another during creation of the integrated circuit. An apparatus for aligning a mask having an image and at least one complimentary alignment mark to a substrate having a first surface and a substantially opposing second surface, where the substrate has at least one alignment mark on the second surface.

Abstract: A method for etching a surface of an integrated circuit. A layer of photoresist is applied to the surface of the integrated circuit. The layer of photoresist is exposed and developed, and the surface of the integrated circuit is etched with an etchant that contains chlorine. The surface of the integrated circuit is exposed to tetra methyl ammonium hydroxide to neutralize the chlorine, and rinsed with water.

Abstract: A method and apparatus for repairing and improving the endurance characteristics of process damaged oxide film formed in a semiconductor device involving sonic annealing by vibrating or oscillating a wafer at a predetermined frequency, wave amplitude, and duration. A signal from a frequency generator is amplified by a voltage amplifier and then sent to a speaker or other acoustic device for the production of vibrating acoustical wave energy. This acoustical wave energy is then directed at a submicron device wafer during a specified time period in order to anneal the gate oxide and, thereby, improve the characteristics of the oxide film.

Abstract: A method of planarizing a first side of a semiconductor wafer with a polishing system includes the step of polishing the first side of the wafer in order to remove material from the wafer. The method also includes the step of moving a lens of a confocal optical system between a number of lens positions so as to maintain focus on the first side of the wafer during the polishing step. The method further includes the step of determining a rate-of-movement value based on movement of the lens during the moving step. Moreover, the method includes the step of stopping the polishing step if the rate-of-movement value has a predetermined relationship with a movement threshold value. An apparatus for polishing a first side of a semiconductor wafer is also disclosed.

Abstract: High energy implantation through varying vertical thicknesses of one or more films is used to form a vertically modulated sub-collector, which simultaneously reduces both the vertical and lateral components of parasitic collector resistance in a vertically integrated bipolar device. The need for a sinker implant or other additional steps to reduce collector resistance is avoided. The necessary processing modifications may be readily integrated into conventional bipolar or BiCMOS process flows.

Abstract: A method of planarizing a first side of a semiconductor wafer with a polishing system includes the step of polishing the first side of the wafer in order to remove material from the wafer. The method also includes the step of moving a lens of a confocal optical system between a number of lens positions so as to maintain focus on the first side of the wafer during the polishing step. The method further includes the step of determining a rate-of-movement value based on movement of the lens during the moving step. Moreover, the method includes the step of stopping the polishing step if the rate-of-movement value has a predetermined relationship with a movement threshold value. An apparatus for polishing a first side of a semiconductor wafer is also disclosed.

Abstract: A method of polishing a first layer of a semiconductor wafer down to a second layer of the semiconductor wafer is disclosed. One step of the method includes polishing the first layer of the semiconductor wafer with a polishing surface having a chemical slurry positioned thereon. The polishing step causes an infrared spectrum to be emitted through the semiconductor wafer. Another step of the method includes detecting a rate of change of intensity level of the infrared spectrum and generating a control signal in response thereto. The method also includes halting the polishing step in response to generation of the control signal. Polishing systems are also disclosed which determine a polishing endpoint for a semiconductor wafer based upon an infrared spectrum generated due to a chemical slurry reacting with the semiconductor wafer.

Abstract: Techniques for fabricating integrated circuits having devices with gate oxides having different thicknesses and a high nitrogen content include forming the gate oxides at pressures at least as high as 2.0 atmospheres in an ambient of a nitrogen-containing gas. In one implementation, a substrate includes a first region for forming a first device having a gate oxide of a first thickness and a second region for forming a second device having a gate oxide of a second different thickness. A first oxynitride layer is formed on the first and second regions in an ambient comprising a nitrogen-containing gas at a pressure in a range of about 10 to about 15 atmospheres. A portion of the first oxynitride layer is removed to expose a surface of the substrate on the second region. Subsequently, a second oxynitride is formed over the first and second regions in an ambient comprising a nitrogen-containing gas at a pressure in a range of about 10 to about 15 atmospheres to form the first and second gate oxides.

Abstract: A method of planarizing a first side of a semiconductor wafer with a polishing system includes the step of polishing the first side of the wafer in order to remove material from the wafer. The method also includes the step of moving a lens of a confocal optical system between a number of lens positions so as to maintain focus on the first side of the wafer during the polishing step. The method further includes the step of determining a rate-of-movement value based on movement of the lens during the moving step. Moreover, the method includes the step of stopping the polishing step if the rate-of-movement value has a predetermined relationship with a movement threshold value. An apparatus for polishing a first side of a semiconductor wafer is also disclosed.

Abstract: A method of planarizing a semiconductor wafer to a distance from a semiconductor substrate of the wafer is disclosed. The method includes the step of forming in the wafer a metallic reporting substance that is at the predetermined distance from the substrate of the wafer. The method also includes the step of polishing a first side of the wafer in order to remove material from the wafer. The method further includes the step of utilizing an atomic absorption spectroscopic technique to detect the presence of the metallic reporting substance in the material removed from the wafer. Moreover, the method includes the step of terminating the polishing step in response to the detection of the metallic reporting substance. An associated apparatus for polishing a semiconductor wafer down to a metallic reporting substance of the wafer is also described.

Abstract: The present invention provides a method for manufacturing a semiconductor device on a substrate. The process involves denuding the substrate by heating to create a denuded zone within the substrate. A screen oxide layer is formed prior to implanting ions into the substrate. This oxide layer remains during the implantation step. The screen oxide layer is removed when forming gates for the semiconductor device.

Abstract: A method of polishing a first layer of a semiconductor wafer down to a second layer of the semiconductor wafer is disclosed. One step of the method includes heating a back surface of the semiconductor wafer to a first temperature level so as to cause a front surface of the semiconductor wafer to have a second temperature level. Another step of the method includes polishing the semiconductor wafer whereby material of the first layer is removed from the semiconductor wafer. The polishing step causes the second temperature level of the front surface to change at a first rate as the material of the first layer is being removed. The method also includes the step of halting the polishing step in response to the second temperature level of the front surface changing at a second rate that is indicative of the second layer being polished during the polishing step. Polishing systems are also disclosed which detect a polishing endpoint for a semiconductor wafer based upon heat conducted through the semiconductor wafer.

Abstract: A technique for reducing silicon defect induced transistor failures, such as latch-up, in a CMOS or other integrated circuit structure includes fabricating the integrated circuit structure on a substrate and implanting a buried layer beneath a surface of the integrated circuit. The buried layer implant is the final implanting step during fabrication of the integrated circuit structure. In another technique, fabricating the integrated circuit structure includes performing multiple sequential processes some of which are performed at elevated temperatures above about 500.degree. C. A buried layer is implanted beneath a surface of the integrated circuit. After implanting the buried layer, the substrate is subjected to a fabrication process at an elevated temperature above about 800.degree. C. only once. Propagation of defects, such as in-the-range defects or ion enhanced stacking faults, from the buried layer to other device layers during the fabrication process is reduced.

Abstract: A method for fabricating a semiconductor device in a substrate. Active regions are defined within the substrate using a thin oxide layer and a silicon nitride layer with portions of the silicon nitride layer being etched away to expose the thin oxide layer. Field oxide regions are formed over regions other than the defined active regions. These field oxide regions are located between the active regions. The remaining portions of the silicon nitride layer and the thin oxide layer are removed and a sacrificial oxide layer is then grown on the surfaces of the active regions. A first mask, a N-well mask, is formed for implanting N-type dopants. A buried layer implanted using P-type dopants with the first mask in place. Thereafter, the N-well regions are implanted. The first mask is removed and a second mask is formed to define regions for implanting P-well regions using P-type dopants. The P-well regions are implanted using P-type dopants.

Abstract: High energy implantation through varying vertical thicknesses of one or more films is used to form a vertically modulated sub-collector, which simultaneously reduces both the vertical and lateral components of parasitic collector resistance in a vertically integrated bipolar device. The need for a sinker implant or other additional steps to reduce collector resistance is avoided. The necessary processing modifications may be readily integrated into conventional bipolar or BiCMOS process flows.

Abstract: A floating breakwater made up of an array of interlocking annular buoyant members of noncorrosive material and including a method of splicing scrap vehicle tires using only tire material or other nondeteriorating material to construct said array of interlocking tires.